# IQ Power Level Trigger - 1 spc - 18 bit Legacy (Clock-Driven Logic)

Creates triggers based on the value of the configuration parameter and the power of the input data.

## reset

A Boolean that clears all internal states on the cycle or call for which this signal is TRUE.

## input data

The complex fixed point <±,18,1> data, with overflow. Wire the output data of an upstream node to this input to transfer data from the upstream node to this node.

## configuration

Conditions for creating triggers.

### trig rising edge

A Boolean that specifies if the output trigger is sensitive to the increase or decrease of the input data power with respect to the trig level. A value of TRUE creates triggers when the input data power level rises above the trig level threshold, and a value of FALSE creates triggers when the input data power level falls below the trig level threshold.

### min quiet time

Minimum quiet time of the input data power with respect to the trig level threshold, in units of valid samples. If the power of input data crosses the trig level threshold before the minimum quiet time has expired, the trigger is ignored and the min quiet time state is reset. The minimum min quiet time value is one valid sample, and a minimum quiet time of zero is coerced to a value of one internally.

### trig level

Threshold for the input data power. It is specified in the units of normalized watts (load impedance = 1 ohm and input data is in volts). The power of the input data is calculated using the following formula: signal power = (input data.I)^2 + (input data.Q)^2

A Boolean that specifies whether the downstream node that is accepting the trigger output is ready to receive a trigger. While the ready for trigger input is FALSE, a trigger is not produced.

## input valid

A Boolean that specifies whether the next input data sample has arrived for processing. Wire the output valid output of an upstream node to this input to transfer data from the upstream node to this node.

## output data

The output complex fixed point <±,18,1> data with overflow. output data is a delayed copy of input data to compensate for the pipeline delay of the trigger indicator. Wire this output to the input data input of a downstream node to transfer data from the node to the downstream node.

## trigger

The active high output that indicates when a trigger has occurred. The trigger output pulses high for a single clock cycle and corresponds to the output data.

## output valid

A Boolean that returns TRUE if this node has computed a result that downstream nodes can use. Wire this output to the input valid input of a downstream node to transfer data from the node to the downstream node.

Where This Node Can Run:

Desktop OS: none

FPGA: All devices