Table Of Contents

ni579x FPGA Self Synchronization (G Dataflow)

Last Modified: January 9, 2017

Use this synchronization method in conjunction with ni579x FPGA Align on the FPGA to synchronize the FPGAs.

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Register Buses

Specifies the Register Buses to which the Synchronization library is connected in the FPGA nodes.

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sync.cptr.period

The period, in clocks, of the Common Periodic Time Reference (CPTR). The CPTR period controls the rate at which synchronized signals are realized. This parameter is required, and you must specify a value for each target to be synchronized. When using ni579x FPGA Align, the CPTR period must be the same as the Reference Clock period. The sync.cptr.period must be set to the ratio of the clock-driven logic (CDL) rate (that the Align node is in) to the sync.meas.Reference Clock rate. For example, the CPTR period must be 13 if you are using PXI_Clk10 for the Reference Clock, and the IO Module\Sample Clock for the CDL clock (130 MHz / 10 MHz). When using ni579x Host Align, this value is configurable. The maximum value is 63. The minimum value for sync.cptr.period must be large enough to ensure transmission across the sync.cptr.FPGA I/O line. Refer to the specifications for the FPGA I/O line that you choose. For example, if the FPGA I/O line has a maximum propagation delay of 50 ns, the minimum value is 7 (the period of the 130 MHz IO Module\Sample Clock is approximately 7.692 ns, so 7 clocks are required to exceed 50 ns). NI does not recommend changing the CPTR period on-the-fly. Alignment must be re-run if you change the CPTR period.

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error in

Error information wired from VIs previously called. Use this information to decide if any functionality should be bypassed in the event of errors from other VIs. Right-click the error in control on the front panel and select Explain Error or Explain Warning from the shortcut menu for more information about the error.

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status

status is TRUE (X) if an error occurred or FALSE (checkmark) to indicate a warning or that no error occurred. Right-click the error in control on the front panel and select Explain Error or Explain Warning from the shortcut menu for more information about the error.

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code

code is the error or warning code. Right-click the error in control on the front panel and select Explain Error or Explain Warning from the shortcut menu for more information about the error.

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source

source describes the origin of the error or warning. Right-click the error in control on the front panel and select Explain Error or Explain Warning from the shortcut menu for more information about the error.

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Register Buses (out)

Passes the Register Buses to the next node.

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error out

Error information. This output provides standard error out functionality.

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status

A Boolean that returns TRUE (X) if an error occurred or FALSE (checkmark) to indicate a warning or that no error occurred.

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code

The error or warning code. If status is TRUE, code is an error code. If status is FALSE, code is 0 or a warning code.

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source

The origin of the error or warning and is, in most cases, the name of the node that produced the error or warning.

Where This Node Can Run:

Desktop OS: Windows

FPGA: Not supported


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