Converts a numeric value to a string that shows the number's engineering format.

Engineering format is similar to exponential format, except the exponent is a multiple of three (..., -3, 0, 3, 6, ...).

A number to be converted into a string.

This input can also be any data type that contains only numbers, such as an array of numbers or a cluster of numbers.

A number specifying how many characters to use to express **number** as a string.

If **width** is less than the number of characters required, this node uses exactly as many characters as needed. If **width** is greater than the number of characters required, this node adds a space on the left side of the output string for each additional character.

**Default: **No value — Exactly as many characters as are needed to represent the number, with no extra padding.

A number specifying the number of digits after the decimal point in the output string. The node rounds **number** to this decimal place.

**Default: **0

A Boolean specifying whether to use the system decimal separator to designate a decimal point.

TRUE | This node uses the localized decimal separator. |

FALSE | This node uses a period as the decimal separator. |

**Default: **FALSE

**number** represented as an engineering string.

The following table shows how the values of
**number**,
**width**, and
**precision** affect
**engineering string**. In this table, the underline character ( _ ) represents a space in
**engineering string**.

number | width | precision | engineering string | Comments |
---|---|---|---|---|

4.93 | 10 | 2 | _ _ _4.93E+0 | number is rounded, padded with spaces on the left. |

.49 | 10 | 2 | _490.00E-3 | number is rounded, padded with a space on the left. |

61.96 | 8 | 1 | _62.0E+0 | number is rounded, padded with a space on the left. |

1789.32 | 8 | 2 | _ 1.79E+3 | number is rounded, padded with a space on the left. |

**Installed By: **LabVIEW Communications System Design Suite (introduced in 1.0)

**Where This Node Can Run: **

Desktop OS: Windows

FPGA: All devices (only within an FPGA Algorithm)