If y is greater than 0, the node shifts x left y bits (from least significant to most significant bit) and inserts zeros in the low-order bits. If y is less than 0, the node shifts x right y bits in the positive direction (from most significant to least significant bit) and inserts zeros in the high-order bits.
An input of any integer representation.
If x is an 8-, 16-, 32-, or 64-bit integer and y is greater than 8, 16, or 32, or 64 or is less than -8, -16, -32, or -64, respectively, the output value is all zeros.
x << y
The result of the shift and same numeric representation as x.
Installed By: LabVIEW Communications System Design Suite (introduced in 1.0)
Where This Node Can Run:
Desktop OS: Windows
FPGA: All devices (only within an FPGA Algorithm)
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