The compiler explores multiple possibilities for the most efficient implementation of an FPGA IP VI on hardware. Exploring the possibilities can lead to long estimation times.
|Keep loop iterations low||
Loops that iterate more than 10,000 times significantly increase estimation times and can sometimes prevent successful compilation.
To address unnecessarily high loop iterations, remove loops from FPGA IP VIs when the loop is not part of the algorithm. For example, if you need to run an algorithm through a large sample set, call the FPGA IP VI from a loop located in a top-level VI instead of incorporating a loop in the algorithm design.
|Share an array across multiple loops||
If your FPGA IP VI has multiple loops, share a common array input across the loops to achieve the fastest estimation times.
|Adjust the throughput and FPGA resource budget||
Throughput and the FPGA resource budget affect the amount of exploration the compiler performs as it tries to find the fastest solution that meets both the throughput and the resource constraints.
To reduce estimation time, increase the FPGA resource budget or lower the specified throughput. You can adjust the throughput and routing margin using the estimation options available on the Configure tab when you select an FPGA IP node from a top-level VI. You can also make the adjustments using the VI Estimation dialog box by clicking FPGA Estimates on the VI tab of an FPGA IP VI.
|Reduce the number of cases in a Case Structure||Implementing Case Structures with more than 50 cases tends to lead to long estimation times. Reduce the number of cases in a Case Structure or reorganize a Case Structure into nested Case Structures to reduce estimation time.|