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When you compile FPGA code, the compiler moves any FPGA IP VIs that are inside of a Case Structure to the outside of the Case Structure. This means that, during development, if you run FPGA code in simulation on the host and FPGA IP VIs are inside of a Case Structure, there will be cycle-level differences between running the VI in simulation on the host and the actual timing once you deploy to hardware. If you want the timing to match more closely between simulation and actual hardware implementation, whenever possible place FPGA IP VIs outside of a Case Structure to model the compiler action.

Example

The following examples demonstrate the modification the compiler makes when you place an FPGA IP VI within a Case Structure.

Note  

When you call an FPGA IP VI from Clock-Driven Logic code, the VI is contained within an FPGA IP integration node.

The following code displays the True and False cases of a Case Structure with the FPGA IP VI inside of it.

The following code displays the True and False cases of a Case Structure with the FPGA IP VI outside of it. This implementation results from either automatic optimizations from the compiler or manual placement of the FPGA IP VI outside the Case Structure, in the scenario that you want your timing to match more closely between simulation and actual hardware implementation.