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Modifies the I/Q data to apply signal impairments. This node must be used inside a Clock-Driven Loop. This node provides the following functionality: data out.I <= (pre-gain offset I + data in.I) * inline gain I + (pre-gain offset Q + data in.Q) * cross gain Q + post-gain offset I data out.Q <= (pre-gain offset Q + data in.Q) * inline gain Q + (pre-gain offset I + data in.I) * cross gain I + post-gain offset Q Where "*" represents scalar multiplication.

Samples Per Cycle (SPC) Use the Function Gallery to change the number of parallel samples used on the 'data in' and 'data out' terminals. For multiple samples per cycle, 'data in' and 'data out' become fixed size arrays of SPC elements. The first element, data[0], is the oldest sample in the array.

Overflows Gain and offset values may cause overflows (signal clipping) to occur. Overflows on 'data in.overflow' are pipelined along with the data path, combined with overflows that occur inside of this node, and output on 'data out.overflow'.

Reset Toggling the 'reset' input high resets the registers in the 'output valid' path, allowing for deterministic startup behavior. The registers in the 'data out' path are not reset, however 'output valid' is held low while 'reset' is asserted and does not assert after reset until the registers in the 'data out' path have been flushed. While reset is asserted, 'ready for input' is held low and 'input valid' is ignored.

Pipeline Delay 4 clock cycles

Approximate resource usage in a Xilinx Virtex-5 or Virtex-6 Slice flip-flops: 325 Slice LUTs: 875 Block RAMs (18kb): 0 DSP48E(1)s: 16

Approximate maximum clock rate in a Xilinx Virtex-5 or Virtex-6 (-1) 160 MHz


Installed By: LabVIEW Communications System Design Suite (introduced in 1.0)

Where This Node Can Run:

Desktop OS: none

FPGA: All devices