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    The NI 5771 ships with the following CLIP items:

    NI 5771 CLIP This CLIP provides access to two analog input channels, eight bidirectional DIO channels, four bidirectional PFI channels, and an input clock selector that can be configured to use one of the following settings:

    • Internal Sample Clock
    • Internal Sample Clock locked to an external Reference Clock through the REF IN connector
    • External Sample Clock through the CLK IN connector
    • Internal Sample Clock locked to an external Reference Clock through IoModSyncClock

    This CLIP also contains an engine to program the ADC and clock circuit, either through predetermined settings for an easier instrument setup or through a raw SPI address and data signals for a more advanced setup. In the LabVIEW FPGA Module, 8-bit analog input data is accessed using a U8 data type. The DIO signals are grouped into two ports of four signals each and are accessed using a U8 data type and Boolean write enable signal. The four PFI signals are accessed individually using Booleans.

    Although real-time sampling is the default sampling mode on the NI 5771, the NI 5771 CLIP also supports Time Interleaved Sampling (TIS) on one analog input channel at a time. TIS enables the device to use both channels on the ADC to sample the same waveform at different relative phases, which increases the real-time sample rate. The NI 5771 then interleaves the samples to create a waveform as if only one ADC channel were sampling the waveform at twice the Sample Clock rate.

    In TIS mode, the data is returned on both the AI 0 <N-7..N> and AI 1 <N-7..N> signals even though the device is only sampling the single AI channel that you selected with the User Data 1 signal. The first sample of data is always AI 1 N–7, regardless of the channel you are sampling. The figure below demonstrates TIS on an NI 5771 device:
    Figure 1. TIS Data Returned on an NI 5771

    The ADC data sheet refers to TIS as Dual-Edge Sampling (DES).