You can enable a programmable debouncing filter on each PFI signal. When the filter is enabled, the controller samples the inputs with a user-configured Filter Clock derived from the controller timebase. This is used to determine whether a pulse is propagated to the rest of the circuit.
However, the filter also introduces jitter onto the PFI signal.
The following is an example of low-to-high transitions of the input signal. High-to-low transitions work similarly.
Assume that an input terminal has been low for a long time. The input terminal then changes from low to high, but glitches several times. When the Filter Clock has sampled the signal high on N consecutive edges, the low-to-high transition is propagated to the rest of the circuit. The value of N depends on the filter setting, as shown in the following table.
|Filter Setting||Filter Clock||Jitter||Min Pulse Width* to Pass||Max Pulse Width* to Not Pass|
|112.5 ns (short)||80 MHz||12.5 ns||112.5 ns||100 ns|
|6.4 μs (medium)||80 MHz||12.5 ns||6.4 μs||6.3875 μs|
|2.56 ms (high)||100 kHz||10 μs||2.56 ms||2.55 ms|
|Custom||User-configurable||1 Filter Clock period||Tuser||Tuser - (1 Filter Clock period)|
|* Pulse widths are nominal values; the accuracy of the controller timebase and I/O distortion will affect these values.|
On power up, the filters are disabled. The figure below shows an example of a low-to-high transition on an input that has a custom filter set to N = 5.