Table Of Contents

Clock Routing

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    Last Modified: May 11, 2018

    The following figure shows the clock routing circuitry of the cRIO-904x.

    Figure 1. Clock Routing Circuitry of the cRIO-904x
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    Note  

    When switching between programming modes, you may notice the terms timebase and clock used interchangeably. This is due to the DAQ ASIC and the RIO FPGA using different terminology for timing and clock mechanisms. The documentation will use the term based on the programming mode discussed.

    80 MHz Timebase

    When programming C Series modules in Real-Time (NI-DAQmx) mode, the 80 MHz timebase can function as the source input to the 32-bit general-purpose counter/timers. The 80 MHz timebase is generated from the onboard oscillator.

    20 MHz and 100 kHz Timebases

    When programming C Series modules in Real-Time (NI-DAQmx) mode, the 20 MHz and 100 kHz timebases can be used to generate many of the analog input and analog output timing signals. These timebases can also function as the source input to the 32-bit general-purpose counter/timers. The 20 MHz and 100 kHz timebases are generated by dividing down the 80 MHz timebase, as shown in the previous figure.

    40 MHz Onboard Clock

    When programming C Series modules in FPGA mode, the 40 MHz onboard clock is used as the top-level clock for your LabVIEW FPGA application and C Series module IO nodes. The 40 MHz onboard clock can be used to clock single-cycle timed loops. Derived clocks of varying frequency can be generated from the 40 MHz onboard clock. The 40 MHz onboard clock is phase aligned with the incoming 80 MHz clock.

    13.1072 MHz, 12.8 MHz, and 10 MHz Timebases and Carrier Clocks

    When programming C Series modules in Real-Time (NI-DAQmx) mode, the 13.1072 MHz, 12.8 MHz, and 10 MHz timebases can be used to generate many of the analog input and analog output timing signals. These timebases can also function as the source input to the 32-bit general-purpose counter/timers. The 13.1072 MHz, 12.8 MHz, and 10 MHz timebases are generated directly from the onboard clock generator.

    When programming C Series modules in FPGA mode, the 13.1072 MHz, 12.8 MHz, and 10 MHz carrier clocks can be used as the master clock for C Series analog input and analog output modules. The 13.1072 MHz, 12.8 MHz, and 10 MHz carrier clocks are available as IO Nodes in LabVIEW FPGA applications and can be used to correlate the onboard clocks with self-timed C Series modules containing free-running clocks.


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