Importing External IP Into LabVIEW FPGA

Publish Date: Oct 08, 2018 | 26 Ratings | 2.77 out of 5 | Print | Submit your review


By incorporating third-party IP into LabVIEW FPGA, you can use a wide range of algorithms that are fine-tuned to Xilinx field-programmable gate arrays (FPGAs) to achieve high performance while taking advantage of code reuse. The LabVIEW FPGA Module offers two methods for importing external IP: the Component-Level Intellectual Property (CLIP) Node and the Intellectual Property Integration Node (IP Integration Node). This white paper examines these two methods.

Table of Contents

  1. Introduction to the CLIP Node
  2. Using CLIP in an FPGA Application
  3. Introduction to the IP Integration Node
  4. CLIP and IP Integration Node Differences
  5. Related Resources

1. Introduction to the CLIP Node

The CLIP Node is a framework for importing existing FPGA IP into LabVIEW FPGA hardware and communicating to it through the LabVIEW FPGA diagram. Once imported, the IP runs independently in parallel with LabVIEW FPGA VI execution. The IP can be in the form of either VHDL or intermediate files such as electronic design interchange format (EDIF) netlists. This feature targets users with some digital design experience and basic knowledge of VHDL, because the IP imported is often written in a lower-level hardware description language ( HDL).

Support for CLIP varies by  FPGA target. Refer to the target hardware documentation for information about CLIP support. Some FPGA targets work with one or both of the following types of CLIP:

User-defined CLIP − Import VHDL code to communicate directly with an FPGA VI.

Socketed CLIP − Import VHDL code to communicate directly with an FPGA VI and with FPGA pins that are not directly exposed to the LabVIEW FPGA Module. Some FPGA targets define a fixed-CLIP socket in the FPGA where you can insert socketed CLIP.

Figure 1. Imported VHDL code in user-defined CLIP Nodes can communicate with an FPGA VI, whereas a socketed CLIP Node allows the IP to interface with both the FPGA VI and available FPGA pins.

For the most up-to-date information, refer to the LabVIEW FPGA Module Help topic titled Using VHDL Code as Component-Level IP (FPGA Module).

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2. Using CLIP in an FPGA Application

The following steps outline the procedure for using CLIP in an FPGA application:

  1. Create or acquire the IP.
  2. Declare the CLIP and define the IP interface in the properties of an FPGA target.
  3. Add CLIP items to the  project.
  4. Use the CLIP items in an FPGA VI.

Create or Acquire the IP

To add CLIP to an FPGA target, you must provide IP in the form of VHDL code to compile into the FPGA target. You can provide the VHDL code in the following ways:

  • Create VHDL.
  • Take advantage of other HDLs such as Verilog by using the Xilinx CORE Generator to create your own compatible cores.
  • Purchase IP from Xilinx or partners.

Note: More than 50 Xilinx IP blocks are in the CORE Generator IP palette in LabVIEW FPGA, which you can incorporate into the dataflow of your LabVIEW FPGA VI without the need to import it using the CLIP or IP Integration Node.

Learn how to Increase IP Reuse With the Xilinx CORE Generator IP Palette.

An important consideration when using CLIP Nodes is the data types supported in LabVIEW FPGA and how they translate to VHDL data types. If your IP uses a logic vector that is not one of the data types listed in Table 1, you need to write a wrapper to extend, cut off, or break up the standard LabVIEW types to fit the data widths of the IP.

Refer to the LabVIEW FPGA Module Help to learn more about other considerations for your IP including using external clocks, crossing clock domains, using synchronization registers, implementing asynchronous resets, and  working with constraints and hierarchy. 

FPGA Module Data Type VHDL Data Type
Boolean std_logic
U8 and I8 std_logic_vector(7 downto 0)
U16 and I16 std_logic_vector(15 downto 0)
U32 and I32 std_logic_vector(31 downto 0)
U64 and I64 std_logic_vector(63 downto 0)
Fixed-point (FXP)

std_logic_vector(x downto 0)

where x is in range [0,63].

Table 1. Data types that are supported for use in the CLIP interface.

Declare the CLIP and Define the IP Interface in the Properties of an FPGA Target

Note: The following example uses the attached simple_and.vhd file to demonstrate how to import IP into a user-defined CLIP Node.

To map the IP inputs and outputs to I/O in LabVIEW, use the FPGA Target Properties Wizard to create an XML file that defines the necessary characteristics of the IP. Follow the steps below to complete this task.

  1. Create a new LabVIEW project with an FPGA target. Right-click the FPGA and select Properties. The Properties dialog contains a section labeled “Component-Level IP.” Click the Create File button to create the XML file

Figure 2. Click “Create File” to begin defining the declaration XML file.

  1. Click the Add Synthesis File… button and browse to the VHDL file that represents the top-level component IP, simple_and.vhd in this case. Proceed by clicking Next.

Figure 3. After adding your IP’s synthesis file, click Next>.

  1. The remainder of the wizard configures the declaration XML file. In this example, navigate the rest of the wizard with the defaults by clicking Next>, validate the Syntax of the imported file, and then click through the remaining Next> buttons.

Figure 4. The generated XML declaration file from the wizard should be listed for the imported IP block.

Once you have finished the Configuring CLIP Wizard, the CLIP declaration name (defined in the XML file) appears alongside the path of the file. In this dialog, you can declare multiple CLIP Nodes for all the different IP blocks you need to import.

Add a CLIP Item to a LabVIEW Project

Declaring the CLIP within the FPGA does not actually add it to the project because you can instantiate multiple instances of one CLIP on the same FPGA. In the next step, you will create an instance of the previously declared  simple AND CLIP item.

  1. Right-click the FPGA target and select New»Component-Level IP. In the CLIP dialog that appears, select the desired CLIP, give this instance a unique name, and select clocks to connect to any lines in the CLIP with the “Clock” signal type. In this example, the latter two options are left as defaults.

Figure 5. This dialog appears when you add an instance of a CLIP to the project. Select the CLIP, define a name, and configure clocks.

  1. Once you click OK from this dialog, this CLIP and all associated inputs and outputs show up in the project in an  entry labeled with the instance name.

Figure 6. This is the project after adding the CLIP, showing all of the I/O point for the IP.

Pass Data Between the CLIP and an FPGA VI

At this point, you are ready to communicate between the CLIP and the FPGA VI. To do so, simply drag and drop the desired I/O point from the project to the FPGA diagram. Your IP should have documentation on how to use the IP. For instance, many IP blocks use some type of handshaking lines for passing data in and out. These are typically labeled “data valid” or “enable.” Use LabVIEW logic to send the correct values at the correct times to exercise the IP. You can place CLIP I/O inside or outside a single-cycle Timed Loop (SCTL), but keep in mind that inside an SCTL, you might have to consider clock domain crossings and use synchronization registers.

Figure 7. To communicate with the CLIP from LabVIEW FPGA, drag and drop the IP inputs and outputs from the project window to the block diagram of the FPGA VI.

Figure 8. The complete LabVIEW FPGA block diagram communicates with IP imported using the CLIP.

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3. Introduction to the IP Integration Node

Note: The IP Integration Node example imports the attached demo_adder.vhd IP block.

  1. Create a new LabVIEW project with an FPGA target and add a new VI under the FPGA target.
  2. In the new VI, drop the IP Integration Node from the Programming palette on the block diagram, save the FPGA VI, and then double-click the node to bring up the wizard dialog.


Figure 9. Double-click on the IP Integration Node to start the import process using the properties wizard.

3. Click on Add Synthesis File… and in the resulting window navigate to and select the demo_adder.vhd file.

4. Back in the wizard dialog, click Next twice without changing the default options.

5. In the file generation step, first check the syntax of the imported VHDL file and then generate the supporting files by clicking the respective buttons as shown below.


Figure 10. The wizard gives you the ability to check the syntax of your VHDL IP before generating the necessary LabVIEW support files.

  1. Once the generation of IP is successful, keep the default options by selecting Next> for the remaining three steps.
  2. On the last step of the wizard, you can select the data types for the different terminals. For this IP block the default fixed-point encoding will suffice. Click Finish to complete the generation.
  3. The IP Integration Node is now configured successfully and ready for you to integrate into the rest of your LabVIEW FPGA application.

Figure 11. The IP Integration Node With Associated IP

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4. CLIP and IP Integration Node Differences

The CLIP and IP Integration Nodes are two ways to import external IP into and you should select between these import methods based on your application. The CLIP Node executes independently and in parallel with your IP developed in LabVIEW FPGA. In addition, CLIP can interface directly with the FPGA clocks and I/O pins. In contrast, the IP Integration Node is inserted into the LabVIEW FPGA block diagram and executes as defined by the dataflow of the LabVIEW VI. As part of the LabVIEW dataflow execution, the IP integration Node gives you the ability to verify the overall application behavior and timing using the cycle-accurate simulation tools.

For more details on the differences between CLIP and the IP Integration Node, refer to the Integrating Third-Party IP (FPGA Module) topic in the LabVIEW Help.


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5. Related Resources

Training and Certification: High-Throughput LabVIEW FPGA

Integrating Third-Party IP (FPGA Module)

Testing and Debugging LabVIEW FPGA Code

Using Xilinx Vivado Design Suite to Prepare Verilog Modules for Integration Into LabVIEW FPGA

Using Xilinx ISE Design Suite to Prepare Verilog Modules for Integration Into LabVIEW FPGA

Compatibility between Xilinx Compilation Tools and NI FPGA Hardware


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