Co-simulation of your FPGA application provides the highest level of abstraction by giving you the ability to create and execute the simulation directly from LabVIEW while making use of a sophisticated third-party cycle-accurate simulator in the background.
In co-simulation, LabVIEW provides stimuli to the IP under test, controls the execution of the simulator, and captures the responses. With LabVIEW co-simulation, a host VI that drives the inputs and execution with normal FPGA host interface functions replaces conventional VHDL-based test benches. This abstraction of the test bench by using your existing LabVIEW skills increases productivity and does not require VHDL expertise to develop and perform cycle-accurate simulations on your LabVIEW FPGA VIs.
Figure 1. Cycle-accurate co-simulation in LabVIEW FPGA removes the need for VHDL expertise with support for test benches written in LabVIEW.
The execution of each FPGA host function determines when the third-party simulator executes the next component of the simulation. For example, when the Write Property Node executes in the LabVIEW host VI, it communicates the appropriate stimuli to the simulator and advances simulation time. Once the simulator has computed the result, it halts execution and waits for the next control command from LabVIEW.
For additional control and flexibility over the simulator execution, the Simulation FPGA host interface palette provides functions to retrieve the current simulation time, forces the simulation to wait for a designated amount of time, or pauses execution of the simulator.
Figure 2. The Simulation FPGA host interface palette exposes functions for more granular control over the third-party simulator execution time.
Co-simulation with LabVIEW test benches is supported with Mentor Graphics ModelSim and Mentor Graphics Questa Advanced Simulator. For a step-by-step tutorial, view Cycle-Accurate Co-Simulation With LabVIEW and Mentor Graphics Simulators.