The SPI serial bus was originally established by Motorola. Today, it is one of the most common communication buses used by integrated circuit manufactures for device to processor or FPGA control. Examples include ADCs, DACs, sensors, and board-only products. Although it is not regulated as a standard by IEEE or another organization, most devices adhere to common set of rules described in this document.
SPI is a synchronous serial data link that operates in full duplex. That is, signals carrying data go in both directions simultaneously. Devices communicate using a master/slave protocol, in which the master starts the data frame. When the master generates a clock then selects a slave device, data may be transferred in either or both directions simultaneously. It is up to the master and slave devices to know whether a received byte is meaningful. This may require a device to discard the received byte in a "transmit only" frame or generate a dummy byte for a "receive only" frame.
The four typical SPI signals include:
Figure 1: Master connected to one slave.
Figure 2: Master connected to multiple slaves. Notice the bank of Chip select lines connected to the individual slaves to enable communication with one at a time.
Figure 3: Statechart of the basic SPI transmission
Parameters called clock polarity (CPOL) and clock phase (CPHA) determine the edges of the clock signal on which the data are driven. These two parameters have two possible states, which allows for four possible combinations, all of which
are incompatible with one another. A master/slave pair must use the same parameter pair values to communicate. If multiple slaves are used that are fixed in different configurations, the master will have to re-configure itself each time it needs to communicate with a different slave
Figure 4: This figure shows the four combinations of CPOL and CPHA and how they affect the polarity of the SCLK line and the edge on which the devices sample the MISO and MOSI lines.
All hardware devices that can communicate using SPI have timing boundaries which give tolerances for the speed, setup, and hold times of each signal. A typical device has the important signal specified like the example in the images below.
Figure 5: This figure show the different signal timing characteristic that usually have tolerances specified on a data sheet.
Figure 6: This table is a example of hardware specifications for Min and Max times for the clock speed, setup, and hold time.
The RMC Digital IO Capabilities white paper provides a detailed example of timing analysis for synchronous interfaces such as SPI.
You have a number of options from National Instruments for communicating using SPI. VI Package Manager hosts IP libraries for NI hardware programmable with LabVIEW FPGA. Software drivers have also been created for Digital I/O and Multifunction Data Acquisition devices, and the USB-845X SPI devices to communicate SPI directly from a PC or Real-Time system. The table below links to detailed information regarding SPI with appropriate hardware and software tools.
|Software Reference||NI Hardware||Description|
|LabVIEW FPGA SPI IP - VIPM||NI Hardware Programmable with LabVIEW FPGA||Download LabVIEW FPGA SPI IP from the VI Package Manager. This FPGA IP works for any hardware enabled by the LabVIEW RIO architecture, including R Series, CompactRIO, Single-Board RIO, and FlexRIO.|
|SPI for Hardware-timed Digital I/O Boards||Digital I/O Hardware Products|
Tutorial and SPI driver code for hardware-timed Digital I/O boards like the 6547, 6548, 6551, 6552, and 6556 devices to communicate using the SPI protocol
|SPI for USB-8451 SPI/I2C USB Device||LabVIEW example and a tutorial for using the USB-8451 or USB-8452 to communicate with SPI devices|