Adapting the Sample Project to Your Hardware
The FPGA VI in this sample project is compiled for specific FPGA and I/O hardware. If you have a different FPGA or different C Series modules, you must adapt this sample project to your hardware. The following steps refer to NI CompactRIO devices, but you also can adapt this sample project to an NI Single-Board RIO device.
- Ensure all devices are configured and connected to the same network as the development computer.
- In the Project Explorer window, add or discover your RT CompactRIO target to the to the top-level project item.
- Add or discover your CompactRIO chassis to the RT Compact RIO target you added in the previous step. Ensure the chassis is set to LabVIEW FPGA Interface mode.
- Add or discover your FPGA target to the CompactRIO chassis you added in the previous step. When prompted to deploy settings, click Deploy Later.
- Add or discover your C Series input and output modules to the FPGA target you added in the previous step.
- Drag the following project items from the default RT CompactRIO target to the one you added in step 2:
- Error Handlers folder
- Globals folder
- Support VIs folder
- RT Loops folder
- Type Definitions folder
- Shared Variables.lvlib
- RT Main.vi
- Drag the following project items from the default FPGA target to the one you added in step 4:
- Support VIs folder
- Type Definitions folder
- FPGA Main.vi
- Variable References.ctl
- Delete the default RT CompactRIO Target project item that no longer has any VIs associated with it.
- Re-establish the link between RT Main.vi and the bitfile:
- Open Initialize and Run FPGA VI.vi, located in the Support VIs folder on the RT CompactRIO Target.
- Drag FPGA Main.vi from the Project Explorer window to the Open FPGA VI Reference VI function.
- Open FPGA Main.vi and ensure the FPGA I/O Nodes use the input and output channels you want. For example, you may want an FPGA I/O Node to read from Mod2/AI5 instead of Mod1/AI2. The actual channels you read from and write to depend on your application.
By default, the FPGA I/O Nodes in this VI read from Mod1/AI0–3 and write to Mod2/AO0–3.
- To minimize time spent compiling, make necessary changes, such as defining a control algorithm and defining a safe state, now. You can compile and run the FPGA before making these changes; however, you will have to compile the FPGA VI again afterwards.
Defining a Control Algorithm
Locate the Control (PID) subdiagram of the Case Structure in FPGA Main.vi and modify this subdiagram to apply a control algorithm. This sample project is designed to implement a PID algorithm. By default, this algorithm returns a constant value of 0 on all output channels. You can perform a different algorithm on each individual channel
Defining Safe Values for Hardware Connected to the C Series Modules
Modify the Safe State, Default subdiagram of the Case structure in FPGA Main.vi to write safe values to the output channels. The values you write here should be ones that you know the connected hardware can safely handle. By default, this subdiagram writes a value of 0 to all output channels.
This subdiagram executes in the following situations:
- When FPGA Main.vi first runs
- The watchdog algorithm times out
- An error occurs while reading from or writing to an FPGA I/O channel
- A "Critical" or "Non-Critical" error occurs on the desktop computer or real-time controller
- You click the Switch Target to Safe State, Stop Control, Stop Manual, or Exit button in UI Main.vi
Configuring the Application
In the Project Explorer window, open My Computer»Globals»Global - Configuration Options.vi. Use this VI to configure the following settings:
- If you are programming or testing the application, leave Debugging as TRUE. If you are building an application for deployment, set Debugging to FALSE.
- To change how the often the control algorithm executes, change the Control Period (ticks). The default is 40000 ticks of the FPGA clock.
- To change the time period during which both endpoints of a network stream must be established, change the Network Stream Connect Timeout (ms). The default is 5000 ms.
- To change how often the real-time controller polls the user interface for commands, change the Network Stream Polling Timeout (ms). The default is 500 ms.
- To change how often the real-time controller pets the watchdog, change the Watchdog Pet Rate (ms).The default is 100 ms.
- To change how long the FPGA has to respond to a watchdog pet, change the Timeout Period (ticks). The default is 40000000 ticks of the FPGA clock.
- To change how often the user interface updates with monitoring and health information from the CompactRIO device, change the Monitoring Loop Rate (ms). The default is 200 ms.
- To change the time period during which identical errors are considered duplicates, change the Error Log Duplicate Interval (ms). This control defines the interval of time during which only the first in a series of identical errors will be logged. For example, if an error occurs after 2000 ms have elapsed and occurs again after 5000 ms have elapsed, and Error Log Duplicate Interval (ms) is 6000 ms, the second occurrence is considered a duplicate and not logged. Only 3000 ms have elapsed, not the 6000 ms required to treat the second error as unique.
The default is 5000 ms.
- To change the names of the network streams, modify the UI Stream Name or RT Stream Name controls. These names affect the endpoint URLs but otherwise have no impact on the application.
- To change the location of the error log file, set the RT Error Log control. The default is c:\logs\logs.txt.
- To change the maximum size of the error log, change the Error Log Max Size (bytes) control. The default is 100000 bytes.