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Home Support Documentation Bugs

LabVIEW NXG 4.0 FPGA Module Known Issues

Updated Mar 10, 2020

Overview

This document contains the LabVIEW NXG 4.0 FPGA Module known issues that were discovered before and since the release of LabVIEW NXG 4.0 FPGA Module. Not every issue known to NI will appear on this list; it is intended to only show the severe and more common issues that can be encountered.

Known Issues

The following items are known issues in LabVIEW NXG 3.1 FPGA Module.

709263—Renaming an FPGA Application breaks associated Open FPGA VI Reference nodes referencing that application
731891—After software installation on LinuxRT targets, RIO server requires a manual restart or additional reboot
744863—Errors outside of Clock-Driven Logic can incorrectly refer to the source of the error as an Optimized FPGA VI.


IDKnown Issue
709263

Return		Renaming an FPGA Application breaks associated Open FPGA VI Reference nodes referencing that application
Renaming an FPGA Application breaks associated Open FPGA VI Reference nodes referencing that application because the 'Rename and Update' dialog fails to automatically update the reference to use the new name.

Workaround: Manually point the Open FPGA VI Reference to the correct FPGA Application.

Reported Version: 3.0  Resolved Version: N/A  Added: 10/29/2018
731891

Return		After software installation on LinuxRT targets, RIO server requires a manual restart or additional reboot
If RIO server is enabled, remote FlexRIO devices may be targeted via the RIO server. After SW installation, this service is not fully configured and requires an additional reboot or manual restart to be fully setup.

Workaround: After the required reboot post SW installation, reboot your target again.
Alternatively, run the following commands to manually restart the service:
/etc/init.d/nirioserver stop
/etc/init.d/nirioserver start

Reported Version: 3.1  Resolved Version: N/A  Added: 05/20/2019
744863

Return		Errors outside of Clock-Driven Logic can incorrectly refer to the source of the error as an Optimized FPGA VI.
Some errors outside of Clock-Driven Logic can incorrectly refer to "Optimized FPGA VI" as the source of the error. One example is an un-initialized shift register on a For Loop.

Workaround: Double-click the error to be taken to the actual error source.
Reported Version: 4.0  Resolved Version: N/A  Added: 10/30/2019
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Glossary of Terms

 

  • Bug ID - When an issue is reported to NI, you may be given this ID or find it on ni.com.  You may also find IDs posted by NI on the discussion forums or in KnowledgeBase articles.
  • Legacy ID – An older issue ID that refers to the same issue.  You may instead find this issue ID in older known issues documents.
  • Description - A few sentences which describe the problem. The brief description given does not necessarily describe the problem in full detail.
  • Workaround - Possible ways to work around the problem.
  • Reported Version - The earliest version in which the issue was reported.
  • Resolved Version - Version in which the issue was resolved or was no longer applicable. "N/A" indicates that the issue has not been resolved.
  • Date Added - The date the issue was added to the document (not the reported date).