When designing and implementing a TSN distributed measurement system, you should consider a few factors that can impact network synchronization accuracy. These include the topology chosen for the distributed application, the quality of the IEEE 802.1AS grand master (GM) clock selected in the IEEE 802.1AS subnet, and the timing architectures of the I/O channels used within the synchronized application.
Synchronized distributed measurement systems are typically made up of multiple nodes. How these nodes are connected depends on which topology you use. The three basic topologies for synchronized distributed measurement systems are line, ring, and star.
Image 1: Line Topology
Image 2: Ring Topology
Image 3: Star Topology
When using TSN to synchronize the devices on the network, a common notion of time is distributed between all the devices in a given topology. As the number of devices increase in a line within the topologies, the number of bridges participating in synchronization increases. Each bridge adds tens of nanoseconds of uncertainty into the synchronization accuracy.
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Because clocks cannot be shared directly over the network, TSN-based devices synchronize by measuring and adjusting the relationship between their clock and a reference clock on the network. In the IEEE 802.1AS specification, the reference clock, referred to as the grand master (GM) clock, is selected automatically through an election algorithm. The election is based on clock quality, traceability, and priority; if there happens to still be a tie after those are announced, then it comes down to the MAC address of the device.
The GM clock has a stability specification that may include phase noise and/or Allan deviation. All other TSN devices in the subnet have a similar specification and also frequently adjust their clock to follow the GM clock, introducing additional low-frequency phase noise.
Learn more about the impact of the GM clock and how to achieve high-accuracy measurements with NI-DAQmx-based TSN devices.
I/O Timing Architectures
To offer a broad range of high-quality measurements, C Series modules and FieldDAQ devices are supported using different types of timing architectures that are separated into two main groups: sample clock timed and oversample clock timed. Mixing these modules can have an impact on synchronization accuracy.
Sample clock-timed modules operate from a sample clock generated by a timing engine on the chassis. Based on the design, these clocks are phase aligned with the rest of the TSN subnet. The timing of the acquisition or generation operation is determined by digital delays in the timing engine and on the module itself.
Scanned modules are types of sample clocked-timed modules that contain a single analog-to-digital converter (ADC) for all channels. Scanned modules add per-channel delays as the single ADC must operate separately for each channel being acquired. When synchronizing scanned modules with nonscanned modules, care must be taken to associate samples from the scanned module and other module types.
Oversample clock-timed modules operate from high-precision clocks that run constantly. On the cDAQ-9185/9189 Ethernet chassis with TSN, these clocks are generated on the chassis itself and tuned to match other chassis clocks but are not phase aligned. These clocks do not drift from each other but could be misaligned by up to a half of a sample period between chassis. Because the clocks run constantly, another signal is required to synchronize the data from these clocks, the sync pulse. This signal indicates when the module should start producing or consuming data. Without this signal, the clock would be synchronized to the network but not the data. NI-DAQmx-based TSN devices can use time as the sync pulse to simplify distributed system development.
Learn more about how to achieve highly accurate measurements from NI-DAQmx-based TSN devices.
Learn more about synchronizing analog input C Series modules with NI-DAQmx.