Digital patterns are composed of both digital states (such as 0, 1, Z) and timing information. Although you have many ways to represent these digital patterns, as long as the digital states and timing information are identical, the resulting digital pattern will also be identical. This, of course, does not mean all digital test equipment is capable of generating these patterns because each tester has its own features and limitations; however, ignoring tester-specific limitations, you have multiple ways to represent a digital pattern. Consider the pattern in Figure 5:
Figure 5. Digital Pattern Timing Diagram
If you represent this digital pattern as a timing set and digital data, tset1 could be defined as
Given the above definition for tset1, the digital data could be defined as a list of vectors or as a scan chain.
Instead of using timing sets, you could oversample the data and specify that the pattern run at a certain rate. For the above pattern, sampling once every 50 ns (20 MHz) reconstructs the waveform without having to modify signal timing. Assuming a clock rate of 20 MHz, the digital pattern could be represented as
As stated above, all of these methods represent the same digital pattern shown in Figure 5. Again, this does not imply that all testers can generate this pattern; rather, you can use several methods to represent a digital pattern.
To further understand NI PXIe-6556 capabilities, consider the following timeplates taken from a WGL file:
For those not familiar with the timing definition of a WGL file,
D = Logic 0 S = Apply pattern data x = Mask output (don’t care) Q = Expect pattern data
Although the NI PXIe-6556 does not support timing sets, as discussed above, you can use oversampling and deep onboard memory to represent the digital vectors. The first step when oversampling a pattern is to determine the desired clock rate. For best resource utilization, you should use the lowest clock rate that meets your needs. For tp1, each output transitions at X*(5 ns) + C, where X is an integer and C is a constant offset for each output channel. The same is true for the input channels because each transitions at X*(5 ns) + C, and, again, C is a constant value for each input channel.
Because all channels are a multiple of 5 ns plus an offset, you can set the clock rate to 1/(5 ns) or 200 MHz. To achieve the offset, C value, you need to configure the position delay to the appropriate value. Delay values are shown in the chart below.
1The WGL file defines signal direction from a device perspective. The NI cards define a signal direction from a board perspective. This means that HSDIO naming is the opposite of the WGL file (input maps to generation and output to acquisition).
Applying the delay values above, the NI PXIe-6556 can generate any pattern using the tp1 timeplate.
Achieving a 100 ns Timeplate Period
Because the onboard clock is running at 200 MHz, each NI PXIe-6556 sample is output for 5 ns. To build a pattern that is 100 ns long, you need 20 samples. Thus, each vector defined in the WGL file is represented by 20 samples on the NI PXIe-6556.
Implementing Timing Sets for the GPIO Lines
As stated above, each sample lasts 5 ns and each WGL file vector is represented by 20 samples. Taking this and the delay chart from above into account, the following table shows the values of the 20 samples needed to compose a vector from the WGL file for each of the GPIO lines.
1 The NI PXIe-6556 can drive 0, 1, and Z logic. The D states should be replaced by the values as defined in the digital vectors.
2 The NI PXIe-6556 can drive 0, 1, and Z logic. The P state should be replaced by the previous value as defined in the digital vectors.
3 The NI PXIe-6556 can compare with L, H, and X states. The Q states should be replaced by the values defined in the digital vectors.
To show that this timing set has been implemented correctly, examine GPIO_3. When the NI PXIe-6556 is generating data, the logic changes after one period (5 ns) and holds the current value for the remaining 95 ns. This is the same as the timeplate defined in the WGL file. When comparing data, the NI PXIe-6556 ignores all data except the 11th and 12th samples. Keeping in mind the acquisition has been delayed 1 ns, this value is compared at 11*(5 ns) + (1 ns) or 56 ns, and again at 12*(5 ns) + (1 ns) or 61 ns. At all other times, 0 ns through 56 ns and 66 ns through 100 ns, the value is an X as defined by the timeplate.
Now suppose a digital pattern uses tp2. You could go through the same process as tp1. Determining the onboard clock rate (1/7.8125 ns) or 128 MHz would be a good selection. Because every value is a multiple of 7.8125 ns, no offset is needed. Using four samples, you can build any of the patterns defined in the WGL file.
What would happen if the WGL file contains vectors using both the tp1 and tp2 timeplates? If you run the tp2 patterns with the configuration from tp1, the effective time plate would be
Notice that the period and many of the edges are different from the original values. Although some applications are immune to this change, assume this behavior is unacceptable and try to improve pattern timing.
Ideally, you could increase the onboard clock rate and achieve the resolution you need to accurately represent the two timeplates. In the above case, this is not practical because the NI PXIe-6556 has a 200 MHz maximum clock rate.
Because increasing the clock rate is not an option, you could reconfigure the hardware when switching from tp1 to tp2, and vice versa. The hardware is capable of holding the last value while it is reconfigured. As long as the application and DUT can tolerate a few milliseconds of delay while the hardware is reconfigured, this is a good option.
If the application cannot tolerate a few milliseconds of delay, or if the application switches between tp1 and tp2 often, you could adjust the delay from sample clock rising edge value to split the difference between the two timing sets. Although this is not as accurate as reconfiguring the hardware, it is a good way to increase the accuracy.
Assuming it is acceptable to coerce tp2 to a 30 ns period, you could achieve an edge placement accuracy of ±860 ps. If the application allows all of the tp2 values to be scaled from 32 to 33.3 MHz (30 ns period), you can run patterns using either timing set without further timing adjustments or board reconfiguration.
For those accustomed to specifying timing sets, oversampling may seem like a foreign concept; however, most people do not need to get into the low-level details of oversampling data. You can use converters to change digital data in one format to another format with little input.