The NI PXI-4110 triple-output programmable DC power supply combines traditional linear and switching power technologies by configuring the switcher as a tracking regulator, essentially creating a rail with variable headroom above the programmed output. The end result is a module with two isolated channels, one from 0 to +20 V and the other from 0 to -20 V, and a single nonisolated channel from 0 to 6 V, all capable of putting out up to 1 A per channel. These basic power output specs are complemented by excellent resolution and low noise for the PXI-4110 as a voltage or current source.
The linear output control of the PXI-4110 is depicted in Figure 1. The core technology in the linear stage is the Linear Technologies LT1970 power op amp with adjustable precision current limit. The LT1970 has several advantages for a PXI power supply implementation, not the least of which being its small size and "on the fly" current limit, which is specifically helpful for ATE applications. Traditionally, this was referred to as a "VI control block" because it allowed the output to be constant-voltage or constant-current controlled, depending on the input settings and output load; it was implemented with discrete op amps, diodes and resistors. This VI control block forms the heart and soul of traditional source/measure units (SMUs). Thus, using the LT1970 VI control block helps give the PXI-4110 SMU-like behavior.
Figure 1: The Linear Technology LT1970 is the heart of the PXI-4110 voltage/current control block.
Because more output voltage and current were required than the LT1970 could provide, analog "translator" circuitry was designed to handle the output range. It was necessary to scale both the output control and the measurement in this fashion. Figure 2 shows the basic blocks that represent this dual-direction translation. In the design of this translation, it was important to keep in mind several critical details:
- It is necessary to bring the output all the way to 0 V
- We must be able to measure both voltages and currents all the way to 0 V with submicroampere leakages
- We must sink enough current from any output load or capacitance to maintain good response time even near 0 V
- We must be able to tolerate input overvoltage conditions
Figure 2: The linear regulation stage is designed to source/measure very low voltages and currents.
The LT1970 acts as an op amp to drive the discrete output devices providing the translation to the required output voltages. Using a discrete MOSFET output element for each channel, output current is boosted to more than 10X the capability of the LT1970 at more than 3X the voltage compliance of the LT1970. Likewise, a high-speed op amp/FET combination is used as a current sense translator to bring the voltage appearing across the current shunts back down to within the LT1970 rails. The result is a fast control loop that delivers excellent transient response and stability over a broad range of loads. This current sense translator is also optimized for dynamic range and noise so that it is possible to sense voltages down to 0 V and currents down to submicroampere levels.
On the nonisolated channel 0, the switching converter is a Linear Technology LT1773 boost-buck converter that provides dynamic regulation of its output. The control output of channel 0 is fed back into the LT1773 through signal conditioning, which results in the LT1773 output "floating" over the channel 0 output by a few tenths of a volt. The result is an extremely power-efficient switching design with all the advantages of a linear regulator.
Directly combining the tracking regulator with the output amplifier described above takes care of the nonisolated channel. With isolated channels 1 and 2, the switching regulator consists of a relatively straightforward high-power DC-DC converter operating at about 200 kHz. The input drive to the converter is synthesized by an FPGA that can vary the duty cycle of the drive signal applied to the switching MOSFETs. The FPGA offers the advantage of intelligent soft-start and ramp-up, which "softens" the transient currents drawn from the PXI backplane, thereby allowing the PXI-4110 to operate within the PXI specification.
Although with the isolated channels there is no direct analog feedback path to the switching regulator control due to the galvanic isolation (see Figure 3), an isolated analog-to-digital converter (ADC) and data path already existed for these channels to provide current and voltage read back. This ADC is monitoring the output voltage and current at all times; so if it can be switched to "look at" the raw input rail supplying the linear output amplifier as well, it is possible to use this signal as isolated feedback. The FPGA can then be used to modulate the duty cycle of the FET drive to the DC-DC converters, effectively providing a digitally controlled, software-in-the-loop PID algorithm to manage the preregulated input to the linear stage. All of this can be done using components that were already needed in the design for other reasons. The result is a cost-efficient, flexible design in a 3U PXI module that can be scaled as additional power supply requirements emerge.
Figure 3: The nonisolated channels on the PXI-4110 make use of analog-to-digital converters to control the switching preregulation elements through the same data path as the current/voltage measurement readback.
There are several advantages to using this software-configurable control loop. First, it is possible to anticipate where the preregulator needs to be before the output amplifier attempts to get there. Figure 4 depicts the importance of implementing this correctly. Second, the response can be tailored to optimize system efficiency. Finally, we can tune the control algorithm to optimize performance depending on whether the input power is coming from the PXI backplane or an external source. It is important that the power being drawn from the PXI backplane be carefully managed to meet the PXI power specifications for the overall product.
Figure 4: The PID control algorithm implemented in an FPGA on the PXI-4110 analyzes and corrects for all changes in load or input power to ensure the preregulator power output is sufficient for the linear stage.
NI engineers found that regulating the voltage alone was not sufficient. Instead, they determined that the optimal response was obtained by regulating the power being dissipated in the linear regulator. The reason for this is shown in Figure 5. When lightly loaded and run at low duty cycles, DC-DC converters tend to behave more like current sources than voltage sources. When a sudden load is applied to the output of a current source, the output rapidly falls. Thus, more voltage headroom is required to give the PID time to respond. This is accommodated by using power regulation, which automatically adjusts the output voltage headroom to be much larger under light load conditions.
Figure 5: Power is regulated on the PXI-4110 (as opposed to voltage) to compensate for sharp changes in the load. Sufficient headroom is maintained at all times to prevent "crashes" between the preregulator rail and output voltage.
Another example of this flexibility is optimizing power drawn from the input power supply - in this case the PXI backplane. Because the power available from a PXI chassis is limited, it is necessary to provide an auxiliary power source for applications above 9 W. However, many applications exist for power levels less than 9 W, and in those situations, the customer shouldn't be required to supplement the PXI backplane. Using this approach, different PID set points (resident on the FPGA) are used for powering from the PXI backplane versus an auxiliary source. If more power is needed than is available from the PXI backplane, the PID set points are changed to provide a more optimum tradeoff between efficiency and step response.
The design of the PXI-4110 made extensive use of the LabVIEW graphical programming language to simulate the software PID and then translate the code to VHDL to run on the FPGA. This gave the engineers tremendous flexibility in trying out a variety of ideas quickly as various use cases and output load conditions were identified. For example, to guarantee that the preregulated output could respond to an input step change request, the PID was defaulted to a duty cycle that can accommodate the full output load of 1 A for a preset number of clock cycles. Thus, if the combination of requested output state and output load demand full current, the linear output stage will always have enough headroom to accommodate it. The control block diagram and its exceptions would have been difficult to synthesize without the use of LabVIEW as a simulator and "sandbox."