Cycle-Accurate Simulation in LabVIEW FPGA


As field-programmable gate array (FPGA) applications grow larger and more complex, simulation has increasingly become important to validate IP before committing to a time-intensive compilation process and debugging the design with high-fidelity test coverage. In NI LabVIEW software, you can simulate your application logic for both functionality and timing. Cycle-accurate simulators test the timing constraints of your application by providing a means to validate the signal propagation of your logic. These simulators also give you the ability to test your entire FPGA application because they incorporate both your LabVIEW FPGA and Component-Level IP (CLIP) or IP Integration Node logic. This white paper focuses on LabVIEW FPGA integration with third-party cycle-accurate simulators. To learn more about the functional simulation capabilities of LabVIEW FPGA, refer to LabVIEW FPGA Online Help.


Note: The Mentor Graphics Questa Advanced Simulator is no longer supported as a simulation tool in LabVIEW FPGA as of the LabVIEW 2018 FPGA Module release.

Co-Simulation With LabVIEW and Third-Party Simulator

Co-simulation of your FPGA application provides the highest level of abstraction by giving you the ability to create and execute the simulation directly from LabVIEW while making use of a sophisticated third-party cycle-accurate simulator in the background.

In co-simulation, LabVIEW provides stimuli to the IP under test, controls the execution of the simulator, and captures the responses. With LabVIEW co-simulation, a host VI that drives the inputs and execution with normal FPGA host interface functions replaces conventional VHDL-based test benches. This abstraction of the test bench by using your existing LabVIEW skills increases productivity and does not require VHDL expertise to develop and perform cycle-accurate simulations on your LabVIEW FPGA VIs.

Figure 1. Cycle-accurate co-simulation in LabVIEW FPGA removes the need for VHDL expertise with support for test benches written in LabVIEW.

The execution of each FPGA host function determines when the third-party simulator executes the next component of the simulation. For example, when the Write Property Node executes in the LabVIEW host VI, it communicates the appropriate stimuli to the simulator and advances simulation time. Once the simulator has computed the result, it halts execution and waits for the next control command from LabVIEW.

For additional control and flexibility over the simulator execution, the Simulation FPGA host interface palette provides functions to retrieve the current simulation time, forces the simulation to wait for a designated amount of time, or pauses execution of the simulator.

Figure 2. The Simulation FPGA host interface palette exposes functions for more granular control over the third-party simulator execution time.

Co-simulation with LabVIEW test benches is supported with Mentor Graphics ModelSim and Mentor Graphics Questa Advanced Simulator. For a step-by-step tutorial, view Cycle-Accurate Co-Simulation With LabVIEW and Mentor Graphics Simulators.


Generate Simulation Exports for Use in Third-Party Simulator

The second and lower-level method for cycle-accurate simulation is to generate and export the LabVIEW FPGA simulation to use directly in a third-party simulator. In contrast to co-simulation, this method requires an HDL-based test bench to provide stimuli, control the test execution, and capture/verify outputs. As a result, to use this method with LabVIEW FPGA, you should be familiar with HDL simulators and VHDL. The advantage of using this method is that in addition to Mentor Graphics ModelSim and Questa, you can import these simulation files into the Xilinx ISim or Vivado Simulator cycle-accurate simulators included with LabVIEW FPGA.

Figure 3. After modifying the test bench generated by LabVIEW, you can execute cycle-accurate simulations in ModelSim, Questa, the Vivado Simulator, or ISim.

As part of the Simulation Export, LabVIEW generates a template test bench file customized for your FPGA application. With this harness in place, you can add specific VHDL to exercise your design appropriately.

Figure 4. LabVIEW generates a template VHDL test bench as part of the simulation export files to accelerate your test bench development.

To learn how to generate the simulation files, edit the test bench, and run the simulation in Xilinx ISim or Vivado Simulator, refer to the step-by-step tutorial, Cycle-Accurate Simulation With Xilinx ISim.


To efficiently simulate your FPGA application before compilation and deployment, LabVIEW FPGA provides tools to conduct both functional and cycle-accurate timing simulation. Cycle-accurate simulators can uncover important signal propagation conflicts and undesired interactions between parallel code. Traditionally, this requires special expertise and a time investment often in excess of the original IP development.

Cycle-accurate co-simulation in LabVIEW FPGA using Mentor Graphics ModelSim or Mentor Graphics Questa eliminates the need for VHDL expertise and dramatically reduces test bench development time by taking advantage of your LabVIEW skills.

LabVIEW FPGA is also shipped with a free cycle-accurate simulator. Depending on your FPGA device, this will be Xilinx ISim or the Vivado Simulator. However, in this case, LabVIEW generates a VHDL template test bench that you must be able to modify to exercise the design appropriately.