PXIe Chassis with LabVIEW 2015 and PXIe-7822R
The PXIe-7822R is a reconfigurable I/O (RIO) device that features a user-programmable FPGA for onboard processing and flexible I/O operation. With LabVIEW FPGA, you can individually configure the digital lines as inputs, outputs, counter/timers, PWM, encoder inputs, or specialized communication protocols. You can also program custom onboard decision making that executes with hardware-timed speed and reliability. For this project we are using DIO0 as the PWM out and DIO1 as the PWM in.
The SLSC-12201 is a digital signal conditioning module designed to work with NI Digital Input and output (DIO) devices. The following is a block diagram and a picture of the module.
The module is configurable via the SLSC bus to either be an output or an input. As an output it is able to amplify digital signals based one of two external references (Vsup_x), the output circuitry can also be programmed to operate in 3 modes: push, pull, or push and pull.
As an input the module defaults to pull-down however it is possible to configure an programmable pull up. The input signal threshold is programmable to operate as a standard 5 V TTL input or an extended range with programmable threshold.
The external reference (Vsup_x) can be programmed to one of two banks of 8 channels each.
For this configuration we are using Vsup_1 which is tied to 24V on the JR1 connector on the RTI 12301 connector.
For this project we are using P0.0 as the scaled PWM output and P0.1 as the scaled PWM input.
The RTI-12301 is used to map the signals from the PXIe-7822R module using a standard SHC68-C68-RDIO2 cable to the SLSC-12201 module. This maps the PXIe-7822R DIO0 on the PXIe-7822R to P0.0 on the SLSC-12201 module and maps DIO1 to P0.1.
SLSC-12101 is a prototyping module intended to help SLSC module developers quickly prototype designs. The module is divided into 4 lattice areas where users can build prototype circuits by either soldering components directly on the lattice or mounting a secondary circuit card onto the lattice area.
The module observes all the requirements to meet Level 2-compatibility as defined by the SLSC Module Design Specifications and is routed in such a way that it can also reach Level 1-compatibility if the module developer follows the signaling requirements of a Fully Compatible Rear I/O. These requirements are described in Chapter 11 of the SLSC Module Design Documentation.
The prototyping module has 4 lattice banks which can be used for prototyping as shown in the picture below:
For this example, we have built the circuit shown below on the bank 1 lattice area. The purpose of this circuit is to open or close the SPDT relay simulating an open circuit for our PWM signal. The relay requires 24 V at 15 mA to energize the relay which is supplied by 2N3904 NPN transistor. The transistor is turned on using CPLD pin 23.
The following is the pin mapping used on the SLSC-12101
XJ2: Pin a1 = Scaled PWM output Signal+ » J1 Pin1
XJ2: Pin b1 = Scaled PWM output Signal- » J1 Pin 16
XJ2: Pin d1 = Scaled PWM Input Signal+ Return » J2 Pin3
XJ2: Pin e1 = Scaled PWM Input Signal- Return » J2 Pin18
The RTI 12305 is used to map the signals from an SLSC using a 44pin connector from the front panel of the SLSC module. This is used for wrap around connections like fault insertion or switching.
External Power Supply, HD 44 Cables and HD 44 Connector Blocks
External power is supplied using a 24DVC power supply from NI (PSU 15) and the signals are cabled using 1 to 1 HD 44 cables to a Phoenix HD 44 connector block.