Luc SAURY - ST-ERICSSON
Sébastien CANY - ST-ERICSSON
Fault localization is a key step in failure analysis flow because we can isolate the defective elementary components of an integrated circuit made of hundreds of millions of transistors.
Thermal laser stimulation is a classic localization technique. The principle is to scan a circuit with a thermal laser beam and monitor the variations of an electrical parameter under the local laser stimulation. The goal is to map the most sensitive areas with respect to this parameter, assuming that the spotted regions are likely to point to a physical defect.
The localization tool we use is a PHEMOS-1000 proposed from the Hamamatsu company. This tool allows for the mapping of current or voltage variations. To monitor a more complex parameter, a tester must be inserted between the device under test and the PHEMOS. This technique is called parametric variation mapping (xVM), where x is the monitored parameter.
Real-Time Variation Mapping
Standard xVM implementations are limited by the tester’s portability, the measurable parameters, and the delay of the data transfer between the tester and the fault-isolation tool. Our innovative solution, real-time variation mapping (RTVM), overcomes these limitations by building real-time variation maps of any electrical parameter. It is based on an NI PXI-1036 chassis equipped with an NI PXI-7852R FPGA module and an NI PXI-6652 high-speed digital I/O (HSDIO) module driven by an NI PXI-8102 controller and NI LabVIEW system design software. LabVIEW was selected to develop a dedicated project for each RTVM, including all the subprograms (VIs) running on the FPGA target and the host PC. Generic VIs, such as the subprogram created to display and save the final data, can be reused from one project to another.
A Complex Case Study
The failing circuit is an RF transceiver for mobile phones. The digital output of one receiver channel (I) is showing high drift and distortion. The other channel (Q) is not affected.
The digital output consists of one clock and three data lines interleaved on a double data rate bus. The data must be acquired in real time, and decoded and analyzed. The relevant electrical parameters are the moving averages and the white noise levels of the output channels, respectively called average (AVG) and fast Fourier transform (FFT). The test mode must be regularly reset to avoid AVG parameter clamping at the maximum value because of drift on the I channel.
We analyzed this complex case with all the resources of our PXI solution. The main device is the FPGA module used to acquire and decode I and Q data, to compute AVG and FFT parameters on the two channels and the laser position for X and Y, and to export all the data to the host PC and the fault-isolation tool in real time. The HSDIO module is used to program the test mode and reset the circuit every 20 ms. The host VI manages the data display and save function as well as the configuration of the FPGA and HSDIO modules.
Our Key Developments: Handshake Mode and Digital Maps
The PXI trigger lines allow us to synchronize the FPGA and HSDIO modules in handshake mode. The FPGA sends trigger pulses when the program starts, at the end of each loop, and when new AVG and FFT parameters are available. After a given number of loops, the HSDIO module resets the test mode and notifies the FPGA of the reset by using a third trigger line. The two modules are used simultaneously for the real-time computations (FPGA) and the test-mode programming (HSDIO).
The laser position is computed in the FPGA from the PHEMOS output signals (line trigger and frame trigger). This position (X, Y) and the test parameters (AVG, FFT) are sent by DMA to the host PC. The data is then saved and displayed as intensity graphs. These “digital” maps have several advantages compared to the “analog” maps built by the PHEMOS. First, the final parameter values (digital data) are directly available for the user, whereas the PHEMOS only displays the variations of the parameters as color spots. Second, the digital format allows us to bypass conversion steps linked to the PHEMOS analog input, which improves the signal-to-noise ratio. Finally, several parameters can be saved and displayed from a single acquisition, which significantly reduces the global acquisition time.
Failure Analysis Conclusion
The RTVM development revealed the abnormal behavior of several metal-oxide semiconductor (MOS) transistors directly linked to the failure mode. These MOS transistors are connected to internal metal-oxide metal (MOM) capacitors used in an operational amplifier of the RF device. Because of this successful localization, the root cause of the problem was detected through standard failure analysis techniques: a process defect was observed at the active level below one MOM capacitor, causing a current leakage to the ground. Without the RTVM step, the defect localization would have required us to insulate and test each elementary component of the defective block, which is practically impossible due to the large size of the block (~50,000 µm²).
Key Benefits of the RVTM Solution
The development described in this case study is used to localize parametric defects in integrated circuits. The solution is based on NI PXI FPGA architecture. Because we chose to use NI tools, we experienced the following benefits with this solution:
- Flexible—suitable for any electrical parameter of any chip developed by the company
- Fast—works in real time, even for complex use cases
- Portable—adapted to the lab environment, which means it can be moved from a test bench to a fault-isolation tool
- Efficient because of complementary PXI resources (FPGA, HSDIO)
- Low-cost, compared to standard test equipment generally used for parametric defect localization
This PXI solution is now a key piece of equipment for the ST-Ericsson failure analysis laboratory. It can be used for all new cases linked to complex electrical parametric failures.
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