Use the SMP CPU Pool Utilities API, described below, to define the OS and TS pools during the initial configuration stage of an application. You can obtain the SMP CPU Pool Utilities VIs by downloading the SMP_CPU_Utilities.zip file attached at the bottom of this page. To install the API, extract the contents of the SMP_CPU_Utilities.zip file to the \labview 8.5\user.lib folder on your computer. After you extract the files to the user.lib folder, the SMP CPU Utilities palette appears as a subpalette of the User Libraries palette the next time you launch LabVIEW.
Note: The SMP CPU Pool Utilities API is supported only on multi-CPU RT targets running the ETS Phar Lap operating system with the NI RT Extensions for SMP installed.
Get CPU Loads.vi
Monitors the distribution of load across the CPUs in the system. For each CPU in the system, this VI returns the total load as a percentage of capacity, as well as the percentage of total capacity devoted to interrupt service routines (ISRs), Timed Structures, and all other threads. The Nth element of each array corresponds to the Nth CPU in the system.
Get Number of CPUs.vi
Returns the number of CPUs in the system.
Set CPU Pool Sizes.vi
Sets the number of CPUs in each pool. You can use this VI to define the OS and TS pools by specifying the number of CPUs you want each pool to contain. This VI creates the OS and TS pools as adjacent pools of contiguous CPUs. The OS pool begins at CPU 0 and the TS pool begins where the OS pool ends.
For example, on an eight-CPU system, if you wire a value of 3 to both the OS Pool and TS Pool controls, this VI assigns CPUs 0-2 to the OS pool, CPUs 3-5 to the TS Pool, and leaves CPUs 6-7 reserved for use by Timed Structures configured for manual CPU assignment.
Note: You cannot use this VI to create empty pools or partially overlapping pools. This VI returns an error if you specify an OS pool or TS pool size of 0 or if the OS Pool and TS Pool values you specify add up to more than the number of CPUs available in the system.
Specifying a value of -1 for either pool indicates no size preference for that pool. If you specify a value of -1 for both pools, this VI creates the default pool configuration in which both pools contain every CPU in the system. If you specify a pool size of -1 for one pool, this VI assigns all remaining CPUs to that pool. For example, on a four-CPU system, if you specify a pool size of -1 for the OS pool and a pool size of 2 for the TS pool, this VI assigns CPUs 0 and 1 to the OS pool and CPUs 2 and 3 to the TS pool.
Set CPU Pool Assignments.vi
Assigns CPUs to one of four possible states: OS pool only, TS pool only, both pools, or no pool (reserved). This VI outputs the bit masks that specify the CPUs assigned to each pool. On an N-CPU system, the bits of the bit mask correspond to CPUs 0 through N-1. The right-most bit of each bit mask corresponds to CPU 0 and the left-most bit corresponds to CPU 31 (if such a CPU exists in the system).
The input to this VI is an array of enums. The enum contains the four possible states of a CPU and each element of the array represents a CPU. For example, assuming an eight-CPU system, the array of enums in the figure below assigns CPUs 0, 1, 2 to the OS Pool, CPUs 3 and 6 to be in the TS Pool, and reserves the remaining CPUs.
Set OS Pool.vi
Specifies the set of CPUs contained in the OS pool. The OS mask input is a bit mask in which the right-most bit corresponds to CPU 0 and the left-most bit corresponds to CPU 31. To assign a CPU core to the OS pool, set the value of the corresponding bit to 1. To specify that the OS pool should not contain a particular CPU, set the value of the corresponding bit to 0.
Note: The OS pool must contain at least one valid CPU.
Set TS Pool.vi
Specifies the set of CPUs contained in the TS pool. The TS mask input is a bit mask in which the right-most bit corresponds to CPU 0 and the left-most bit corresponds to CPU 31. To assign a CPU to the TS pool, set the value of the corresponding bit to 1. To specify that the TS pool should not contain a particular CPU, set the value of the corresponding bit to 0.
Note: The TS pool must contain at least one valid CPU.