Release 9.1.03i - xst J.33
Copyright (c) 1995-2007 Xilinx, Inc.  All rights reserved.
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TABLE OF CONTENTS
  1) Synthesis Options Summary
  2) HDL Compilation
  3) Design Hierarchy Analysis
  4) HDL Analysis
  5) HDL Synthesis
     5.1) HDL Synthesis Report
  6) Advanced HDL Synthesis
     6.1) Advanced HDL Synthesis Report
  7) Low Level Synthesis
  8) Partition Report
  9) Final Report
     9.1) Device utilization summary
     9.2) Partition Resource Summary
     9.3) TIMING REPORT


=========================================================================
*                      Synthesis Options Summary                        *
=========================================================================
---- Source Parameters
Input File Name                    : "C:/NIFPGA85/srvrTmp/LOCALH~1/TEST_F~1/toplevel_gen.prj"
Input Format                       : VHDL

---- Target Parameters
Output File Name                   : "toplevel_gen"
Output Format                      : ngc
Target Device                      : xc3s2000-4-fg456

---- Source Options
ROM Extraction                     : YES
RAM Extraction                     : YES
RAM Style                          : Auto

---- Target Options
Global Maximum Fanout              : 150

---- General Options
Optimization Goal                  : SPEED
RTL Output                         : YES
Read Cores                         : YES

=========================================================================

WARNING:Xst:29 - Optimization Effort not specified
The following parameters have been added:
Optimization Effort                : 1

=========================================================================

=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file "C:/NIFPGA85/srvrTmp/LOCALH~1/TEST_F~1/nirvi_ZeroDelayer.vhd" in Library work.
Entity <nirvi_ZeroDelayer> compiled.
Entity <nirvi_ZeroDelayer> (Architecture <rtl>) compiled.
Compiling vhdl file "C:/NIFPGA85/srvrTmp/LOCALH~1/TEST_F~1/arb_rw_0B0CD520_007a.vhd" in Library work.
Entity <arb_rw_0B0CD520_007a> compiled.
Entity <arb_rw_0B0CD520_007a> (Architecture <rtl>) compiled.
Compiling vhdl file "C:/NIFPGA85/srvrTmp/LOCALH~1/TEST_F~1/arb_rw_0B0CC8D8_0079.vhd" in Library work.
Entity <arb_rw_0B0CC8D8_0079> compiled.
Entity <arb_rw_0B0CC8D8_0079> (Architecture <rtl>) compiled.
Compiling vhdl file "C:/NIFPGA85/srvrTmp/LOCALH~1/TEST_F~1/arb_rw_0B0C3710_0078.vhd" in Library work.
Entity <arb_rw_0B0C3710_0078> compiled.
Entity <arb_rw_0B0C3710_0078> (Architecture <rtl>) compiled.
Compiling vhdl file "C:/NIFPGA85/srvrTmp/LOCALH~1/TEST_F~1/arb_rw_0B0C1B48_0077.vhd" in Library work.
Entity <arb_rw_0B0C1B48_0077> compiled.
Entity <arb_rw_0B0C1B48_0077> (Architecture <rtl>) compiled.
Compiling vhdl file "C:/NIFPGA85/srvrTmp/LOCALH~1/TEST_F~1/arb_rw_0B0CE1D0_0076.vhd" in Library work.
Entity <arb_rw_0B0CE1D0_0076> compiled.
Entity <arb_rw_0B0CE1D0_0076> (Architecture <rtl>) compiled.
Compiling vhdl file "C:/NIFPGA85/srvrTmp/LOCALH~1/TEST_F~1/arb_rw_0B0C5CC8_0075.vhd" in Library work.
Entity <arb_rw_0B0C5CC8_0075> compiled.
Entity <arb_rw_0B0C5CC8_0075> (Architecture <rtl>) compiled.
Compiling vhdl file "C:/NIFPGA85/srvrTmp/LOCALH~1/TEST_F~1/PkgNiUtilities.vhd" in Library work.
Package <PkgNiUtilities> compiled.
Package body <PkgNiUtilities> compiled.
Compiling vhdl file "C:/NIFPGA85/srvrTmp/LOCALH~1/TEST_F~1/PkgCommIntConfiguration.vhd" in Library work.
Package <PkgCommIntConfiguration> compiled.
Package body <PkgCommIntConfiguration> compiled.
Compiling vhdl file "C:/NIFPGA85/srvrTmp/LOCALH~1/TEST_F~1/PkgCommunicationInterface.vhd" in Library work.
Package <PkgCommunicationInterface> compiled.
Package body <PkgCommunicationInterface> compiled.
Compiling vhdl file "C:/NIFPGA85/srvrTmp/LOCALH~1/TEST_F~1/CustomArbForMiteIoLikePortOnResInterface.vhd" in Library work.
Entity <CustomArbForMiteIoLikePortOnResInterface> compiled.
Entity <CustomArbForMiteIoLikePortOnResInterface> (Architecture <rtl>) compiled.
Compiling vhdl file "C:/NIFPGA85/srvrTmp/LOCALH~1/TEST_F~1/arb_rw_0AE9A608_0074.vhd" in Library work.
Entity <arb_rw_0AE9A608_0074> compiled.
Entity <arb_rw_0AE9A608_0074> (Architecture <rtl>) compiled.
Compiling vhdl file "C:/NIFPGA85/srvrTmp/LOCALH~1/TEST_F~1/arb_rw_0AFB6A90_0073.vhd" in Library work.
Entity <arb_rw_0AFB6A90_0073> compiled.
Entity <arb_rw_0AFB6A90_0073> (Architecture <rtl>) compiled.
Compiling vhdl file "C:/NIFPGA85/srvrTmp/LOCALH~1/TEST_F~1/TerminalRegister.vhd" in Library work.
Entity <TerminalRegister> compiled.
Entity <TerminalRegister> (Architecture <rtl>) compiled.
Compiling vhdl file "C:/NIFPGA85/srvrTmp/LOCALH~1/TEST_F~1/PkgRegister.vhd" in Library work.
Package <PkgRegister> compiled.
Package body <PkgRegister> compiled.
Compiling vhdl file "C:/NIFPGA85/srvrTmp/LOCALH~1/TEST_F~1/testaviaFPGACompileCopy1result0.vhd" in Library work.
Entity <testaviaFPGACompileCopy1result0> compiled.
Entity <testaviaFPGACompileCopy1result0> (Architecture <rtl>) compiled.
Compiling vhdl file "C:/NIFPGA85/srvrTmp/LOCALH~1/TEST_F~1/ViSignature.vhd" in Library work.
Entity <ViSignature> compiled.
Entity <ViSignature> (Architecture <rtl>) compiled.
Compiling vhdl file "C:/NIFPGA85/srvrTmp/LOCALH~1/TEST_F~1/ViControl.vhd" in Library work.
Entity <ViControl> compiled.
Entity <ViControl> (Architecture <rtl>) compiled.
Compiling vhdl file "C:/NIFPGA85/srvrTmp/LOCALH~1/TEST_F~1/HandshakeBase.vhd" in Library work.
Entity <HandshakeBase> compiled.
Entity <HandshakeBase> (Architecture <behavior>) compiled.
Compiling vhdl file "C:/NIFPGA85/srvrTmp/LOCALH~1/TEST_F~1/HandshakeSLV.vhd" in Library work.
Entity <HandshakeSLV> compiled.
Entity <HandshakeSLV> (Architecture <struct>) compiled.
Compiling vhdl file "C:/NIFPGA85/srvrTmp/LOCALH~1/TEST_F~1/MiteIrq.vhd" in Library work.
Entity <MiteIrq> compiled.
Entity <MiteIrq> (Architecture <rtl>) compiled.
Compiling vhdl file "C:/NIFPGA85/srvrTmp/LOCALH~1/TEST_F~1/FlipFlopFifo.vhd" in Library work.
Entity <FlipFlopFifo> compiled.
Entity <FlipFlopFifo> (Architecture <rtl>) compiled.
Compiling vhdl file "C:/NIFPGA85/srvrTmp/LOCALH~1/TEST_F~1/FifoPopBuffer.vhd" in Library work.
Entity <FifoPopBuffer> compiled.
Entity <FifoPopBuffer> (Architecture <rtl>) compiled.
Compiling vhdl file "C:/NIFPGA85/srvrTmp/LOCALH~1/TEST_F~1/DmaMiteWriteRegs.vhd" in Library work.
Entity <DmaMiteWriteRegs> compiled.
Entity <DmaMiteWriteRegs> (Architecture <RTL>) compiled.
Compiling vhdl file "C:/NIFPGA85/srvrTmp/LOCALH~1/TEST_F~1/DmaDisabler.vhd" in Library work.
Entity <DmaDisabler> compiled.
Entity <DmaDisabler> (Architecture <rtl>) compiled.
Compiling vhdl file "C:/NIFPGA85/srvrTmp/LOCALH~1/TEST_F~1/CpuDataWr.vhd" in Library work.
Entity <CpuDataWr> compiled.
Entity <CpuDataWr> (Architecture <rtl>) compiled.
Compiling vhdl file "C:/NIFPGA85/srvrTmp/LOCALH~1/TEST_F~1/FifoHalfWordWriter.vhd" in Library work.
Entity <FifoHalfWordWriter> compiled.
Entity <FifoHalfWordWriter> (Architecture <rtl>) compiled.
Compiling vhdl file "C:/NIFPGA85/srvrTmp/LOCALH~1/TEST_F~1/DualPortRAM.vhd" in Library work.
Entity <DualPortRAM> compiled.
Entity <DualPortRAM> (Architecture <rtl>) compiled.
Compiling vhdl file "C:/NIFPGA85/srvrTmp/LOCALH~1/TEST_F~1/PkgGray.vhd" in Library work.
Package <PkgGray> compiled.
Package body <PkgGray> compiled.
Compiling vhdl file "C:/NIFPGA85/srvrTmp/LOCALH~1/TEST_F~1/FifoFlags.vhd" in Library work.
Entity <FifoFlags> compiled.
Entity <FifoFlags> (Architecture <rtl>) compiled.
Compiling vhdl file "C:/NIFPGA85/srvrTmp/LOCALH~1/TEST_F~1/Fifo.vhd" in Library work.
Entity <Fifo> compiled.
Entity <Fifo> (Architecture <rtl>) compiled.
Compiling vhdl file "C:/NIFPGA85/srvrTmp/LOCALH~1/TEST_F~1/MiteWriteInterface.vhd" in Library work.
Entity <MiteWriteInterface> compiled.
Entity <MiteWriteInterface> (Architecture <RTL>) compiled.
Compiling vhdl file "C:/NIFPGA85/srvrTmp/LOCALH~1/TEST_F~1/MiteDmaOutput.vhd" in Library work.
Entity <MiteDmaOutput> compiled.
Entity <MiteDmaOutput> (Architecture <rtl>) compiled.
Compiling vhdl file "C:/NIFPGA85/srvrTmp/LOCALH~1/TEST_F~1/DmaMiteReadRegs.vhd" in Library work.
Entity <DmaMiteReadRegs> compiled.
Entity <DmaMiteReadRegs> (Architecture <RTL>) compiled.
Compiling vhdl file "C:/NIFPGA85/srvrTmp/LOCALH~1/TEST_F~1/CpuDataRd.vhd" in Library work.
Entity <CpuDataRd> compiled.
Entity <CpuDataRd> (Architecture <rtl>) compiled.
Compiling vhdl file "C:/NIFPGA85/srvrTmp/LOCALH~1/TEST_F~1/HandshakeBool.vhd" in Library work.
Entity <HandshakeBool> compiled.
Entity <HandshakeBool> (Architecture <struct>) compiled.
Compiling vhdl file "C:/NIFPGA85/srvrTmp/LOCALH~1/TEST_F~1/FifoHalfWordReader.vhd" in Library work.
Entity <FifoHalfWordReader> compiled.
Entity <FifoHalfWordReader> (Architecture <rtl>) compiled.
Compiling vhdl file "C:/NIFPGA85/srvrTmp/LOCALH~1/TEST_F~1/MiteReadInterface.vhd" in Library work.
Entity <MiteReadInterface> compiled.
Entity <MiteReadInterface> (Architecture <RTL>) compiled.
Compiling vhdl file "C:/NIFPGA85/srvrTmp/LOCALH~1/TEST_F~1/MiteDmaInput.vhd" in Library work.
Entity <MiteDmaInput> compiled.
Entity <MiteDmaInput> (Architecture <rtl>) compiled.
Compiling vhdl file "C:/NIFPGA85/srvrTmp/LOCALH~1/TEST_F~1/PulseSyncBase.vhd" in Library work.
Entity <PulseSyncBase> compiled.
Entity <PulseSyncBase> (Architecture <behavior>) compiled.
Compiling vhdl file "C:/NIFPGA85/srvrTmp/LOCALH~1/TEST_F~1/PulseSyncBool.vhd" in Library work.
Entity <PulseSyncBool> compiled.
Entity <PulseSyncBool> (Architecture <behavior>) compiled.
Compiling vhdl file "C:/NIFPGA85/srvrTmp/LOCALH~1/TEST_F~1/PulseSyncBaseWrapper.vhd" in Library work.
Entity <PulseSyncBaseWrapper> compiled.
Entity <PulseSyncBaseWrapper> (Architecture <rtl>) compiled.
Compiling vhdl file "C:/NIFPGA85/srvrTmp/LOCALH~1/TEST_F~1/FifoPortReset.vhd" in Library work.
Entity <FifoPortReset> compiled.
Entity <FifoPortReset> (Architecture <rtl>) compiled.
Compiling vhdl file "C:/NIFPGA85/srvrTmp/LOCALH~1/TEST_F~1/DoubleSyncBase.vhd" in Library work.
Entity <DoubleSyncBase> compiled.
Entity <DoubleSyncBase> (Architecture <behavior>) compiled.
Compiling vhdl file "C:/NIFPGA85/srvrTmp/LOCALH~1/TEST_F~1/DoubleSyncBool.vhd" in Library work.
Entity <DoubleSyncBool> compiled.
Entity <DoubleSyncBool> (Architecture <behavior>) compiled.
Compiling vhdl file "C:/NIFPGA85/srvrTmp/LOCALH~1/TEST_F~1/FifoClearControl.vhd" in Library work.
Entity <FifoClearControl> compiled.
Entity <FifoClearControl> (Architecture <rtl>) compiled.
Compiling vhdl file "C:/NIFPGA85/srvrTmp/LOCALH~1/TEST_F~1/TimeoutManager.vhd" in Library work.
Entity <TimeoutManager> compiled.
Entity <TimeoutManager> (Architecture <rtl>) compiled.
Compiling vhdl file "C:/NIFPGA85/srvrTmp/LOCALH~1/TEST_F~1/MiteDmaComponentEnableChain.vhd" in Library work.
Entity <MiteDmaComponentEnableChain> compiled.
Entity <MiteDmaComponentEnableChain> (Architecture <rtl>) compiled.
Compiling vhdl file "C:/NIFPGA85/srvrTmp/LOCALH~1/TEST_F~1/MiteDmaComponent.vhd" in Library work.
Entity <MiteDmaComponent> compiled.
Entity <MiteDmaComponent> (Architecture <rtl>) compiled.
Compiling vhdl file "C:/NIFPGA85/srvrTmp/LOCALH~1/TEST_F~1/Adapter16.vhd" in Library work.
Entity <Adapter16> compiled.
Entity <Adapter16> (Architecture <rtl>) compiled.
Compiling vhdl file "C:/NIFPGA85/srvrTmp/LOCALH~1/TEST_F~1/RegisterAccess32.vhd" in Library work.
Entity <RegisterAccess32> compiled.
Entity <RegisterAccess32> (Architecture <rtl>) compiled.
Compiling vhdl file "C:/NIFPGA85/srvrTmp/LOCALH~1/TEST_F~1/RegisterAccess.vhd" in Library work.
Entity <RegisterAccess> compiled.
Entity <RegisterAccess> (Architecture <rtl>) compiled.
Compiling vhdl file "C:/NIFPGA85/srvrTmp/LOCALH~1/TEST_F~1/MiteInterfaceOutputEnables.vhd" in Library work.
Entity <MiteInterfaceOutputEnables> compiled.
Entity <MiteInterfaceOutputEnables> (Architecture <rtl>) compiled.
Compiling vhdl file "C:/NIFPGA85/srvrTmp/LOCALH~1/TEST_F~1/MiteInterface.vhd" in Library work.
Entity <MiteInterface> compiled.
Entity <MiteInterface> (Architecture <rtl>) compiled.
Compiling vhdl file "C:/NIFPGA85/srvrTmp/LOCALH~1/TEST_F~1/Interface.vhd" in Library work.
Entity <Interface> compiled.
Entity <Interface> (Architecture <rtl>) compiled.
Compiling vhdl file "C:/NIFPGA85/srvrTmp/LOCALH~1/TEST_F~1/ShiftRegComp.vhd" in Library work.
Entity <ShiftRegComp> compiled.
Entity <ShiftRegComp> (Architecture <rtl>) compiled.
Compiling vhdl file "C:/NIFPGA85/srvrTmp/LOCALH~1/TEST_F~1/bushold.vhd" in Library work.
Entity <bushold> compiled.
Entity <bushold> (Architecture <rtl>) compiled.
Compiling vhdl file "C:/NIFPGA85/srvrTmp/LOCALH~1/TEST_F~1/InvisibleResholder.vhd" in Library work.
Entity <InvisibleResholder> compiled.
Entity <InvisibleResholder> (Architecture <rtl>) compiled.
Compiling vhdl file "C:/NIFPGA85/srvrTmp/LOCALH~1/TEST_F~1/PkgFxp.vhd" in Library work.
Package <PkgFxp> compiled.
Package body <PkgFxp> compiled.
Compiling vhdl file "C:/NIFPGA85/srvrTmp/LOCALH~1/TEST_F~1/NiLvFxpEnableHandler.vhd" in Library work.
Entity <NiLvFxpEnableHandler> compiled.
Entity <NiLvFxpEnableHandler> (Architecture <rtl>) compiled.
Compiling vhdl file "C:/NIFPGA85/srvrTmp/LOCALH~1/TEST_F~1/PkgFxpArithmetic.vhd" in Library work.
Package <PkgFxpArithmetic> compiled.
Package body <PkgFxpArithmetic> compiled.
Compiling vhdl file "C:/NIFPGA85/srvrTmp/LOCALH~1/TEST_F~1/NiLvFxpCoerce.vhd" in Library work.
Entity <NiLvFxpCoerce> compiled.
Entity <NiLvFxpCoerce> (Architecture <rtl>) compiled.
Compiling vhdl file "C:/NIFPGA85/srvrTmp/LOCALH~1/TEST_F~1/mux_level1_forZ_005b.vhd" in Library work.
Entity <mux_level1_forZ_005b> compiled.
Entity <mux_level1_forZ_005b> (Architecture <vhdl_modgen>) compiled.
Compiling vhdl file "C:/NIFPGA85/srvrTmp/LOCALH~1/TEST_F~1/demux_level1_forX_005a.vhd" in Library work.
Entity <demux_level1_forX_005a> compiled.
Entity <demux_level1_forX_005a> (Architecture <vhdl_modgen>) compiled.
Compiling vhdl file "C:/NIFPGA85/srvrTmp/LOCALH~1/TEST_F~1/prim_CVT_Fascade_02C45410_09a2dc60.vhd" in Library work.
Entity <prim_CVT_Fascade_02C45410_09a2dc60> compiled.
Entity <prim_CVT_Fascade_02C45410_09a2dc60> (Architecture <vhdl_labview>) compiled.
Compiling vhdl file "C:/NIFPGA85/srvrTmp/LOCALH~1/TEST_F~1/mux_level1_forZ_0050.vhd" in Library work.
Entity <mux_level1_forZ_0050> compiled.
Entity <mux_level1_forZ_0050> (Architecture <vhdl_modgen>) compiled.
Compiling vhdl file "C:/NIFPGA85/srvrTmp/LOCALH~1/TEST_F~1/demux_level1_forX_004f.vhd" in Library work.
Entity <demux_level1_forX_004f> compiled.
Entity <demux_level1_forX_004f> (Architecture <vhdl_modgen>) compiled.
Compiling vhdl file "C:/NIFPGA85/srvrTmp/LOCALH~1/TEST_F~1/prim_CVT_Fascade_02C45410_0ab39bd0.vhd" in Library work.
Entity <prim_CVT_Fascade_02C45410_0ab39bd0> compiled.
Entity <prim_CVT_Fascade_02C45410_0ab39bd0> (Architecture <vhdl_labview>) compiled.
Compiling vhdl file "C:/NIFPGA85/srvrTmp/LOCALH~1/TEST_F~1/demux_003c.vhd" in Library work.
Entity <demux_003c> compiled.
Entity <demux_003c> (Architecture <vhdl_modgen>) compiled.
Compiling vhdl file "C:/NIFPGA85/srvrTmp/LOCALH~1/TEST_F~1/demux_Fascade_02C45410_0abe80b4.vhd" in Library work.
Entity <demux_Fascade_02C45410_0abe80b4> compiled.
Entity <demux_Fascade_02C45410_0abe80b4> (Architecture <vhdl_labview>) compiled.
Compiling vhdl file "C:/NIFPGA85/srvrTmp/LOCALH~1/TEST_F~1/XNode_h2c45410_n99e944c_0ab3a308.vhd" in Library work.
Entity <XNode_h2c45410_n99e944c_0ab3a308> compiled.
Entity <XNode_h2c45410_n99e944c_0ab3a308> (Architecture <vhdl_labview>) compiled.
Compiling vhdl file "C:/NIFPGA85/srvrTmp/LOCALH~1/TEST_F~1/TimedLoopController.vhd" in Library work.
Entity <TimedLoopController> compiled.
Entity <TimedLoopController> (Architecture <rtl>) compiled.
Compiling vhdl file "C:/NIFPGA85/srvrTmp/LOCALH~1/TEST_F~1/timedLoop_0060.vhd" in Library work.
Entity <timedLoop_0060> compiled.
Entity <timedLoop_0060> (Architecture <rtl>) compiled.
Compiling vhdl file "C:/NIFPGA85/srvrTmp/LOCALH~1/TEST_F~1/XNode_h2c45410_n99e954c_09a2e7f8.vhd" in Library work.
Entity <XNode_h2c45410_n99e954c_09a2e7f8> compiled.
Entity <XNode_h2c45410_n99e954c_09a2e7f8> (Architecture <vhdl_labview>) compiled.
Compiling vhdl file "C:/NIFPGA85/srvrTmp/LOCALH~1/TEST_F~1/demux_001f.vhd" in Library work.
Entity <demux_001f> compiled.
Entity <demux_001f> (Architecture <vhdl_modgen>) compiled.
Compiling vhdl file "C:/NIFPGA85/srvrTmp/LOCALH~1/TEST_F~1/demux_Fascade_02C45410_0acd5af4.vhd" in Library work.
Entity <demux_Fascade_02C45410_0acd5af4> compiled.
Entity <demux_Fascade_02C45410_0acd5af4> (Architecture <vhdl_labview>) compiled.
Compiling vhdl file "C:/NIFPGA85/srvrTmp/LOCALH~1/TEST_F~1/XNode_h2c45410_n99e28cc_0acd9720.vhd" in Library work.
Entity <XNode_h2c45410_n99e28cc_0acd9720> compiled.
Entity <XNode_h2c45410_n99e28cc_0acd9720> (Architecture <vhdl_labview>) compiled.
Compiling vhdl file "C:/NIFPGA85/srvrTmp/LOCALH~1/TEST_F~1/prim_cparith_or3_0_0031.vhd" in Library work.
Entity <prim_cparith_or3_0_0031> compiled.
Entity <prim_cparith_or3_0_0031> (Architecture <rtl>) compiled.
Compiling vhdl file "C:/NIFPGA85/srvrTmp/LOCALH~1/TEST_F~1/prim_cparith_or2_0_0031.vhd" in Library work.
Entity <prim_cparith_or2_0_0031> compiled.
Entity <prim_cparith_or2_0_0031> (Architecture <rtl>) compiled.
Compiling vhdl file "C:/NIFPGA85/srvrTmp/LOCALH~1/TEST_F~1/prim_cparith_or1_1_0031.vhd" in Library work.
Entity <prim_cparith_or1_1_0031> compiled.
Entity <prim_cparith_or1_1_0031> (Architecture <rtl>) compiled.
Compiling vhdl file "C:/NIFPGA85/srvrTmp/LOCALH~1/TEST_F~1/prim_cparith_or1_0_0031.vhd" in Library work.
Entity <prim_cparith_or1_0_0031> compiled.
Entity <prim_cparith_or1_0_0031> (Architecture <rtl>) compiled.
Compiling vhdl file "C:/NIFPGA85/srvrTmp/LOCALH~1/TEST_F~1/prim_cparith_or0_3_0031.vhd" in Library work.
Entity <prim_cparith_or0_3_0031> compiled.
Entity <prim_cparith_or0_3_0031> (Architecture <rtl>) compiled.
Compiling vhdl file "C:/NIFPGA85/srvrTmp/LOCALH~1/TEST_F~1/prim_cparith_or0_2_0031.vhd" in Library work.
Entity <prim_cparith_or0_2_0031> compiled.
Entity <prim_cparith_or0_2_0031> (Architecture <rtl>) compiled.
Compiling vhdl file "C:/NIFPGA85/srvrTmp/LOCALH~1/TEST_F~1/prim_cparith_or0_1_0031.vhd" in Library work.
Entity <prim_cparith_or0_1_0031> compiled.
Entity <prim_cparith_or0_1_0031> (Architecture <rtl>) compiled.
Compiling vhdl file "C:/NIFPGA85/srvrTmp/LOCALH~1/TEST_F~1/prim_cparith_or0_0_0031.vhd" in Library work.
Entity <prim_cparith_or0_0_0031> compiled.
Entity <prim_cparith_or0_0_0031> (Architecture <rtl>) compiled.
Compiling vhdl file "C:/NIFPGA85/srvrTmp/LOCALH~1/TEST_F~1/cpdarith_0031.vhd" in Library work.
Entity <cpdarith_0031> compiled.
Entity <cpdarith_0031> (Architecture <vhdl_modgen>) compiled.
Compiling vhdl file "C:/NIFPGA85/srvrTmp/LOCALH~1/TEST_F~1/scTunnel_0030.vhd" in Library work.
Entity <scTunnel_0030> compiled.
Entity <scTunnel_0030> (Architecture <rtl>) compiled.
Compiling vhdl file "C:/NIFPGA85/srvrTmp/LOCALH~1/TEST_F~1/rvi_test_vi_FPGACompileCopy1_0a278380.vhd" in Library work.
Entity <rvi_test_vi_FPGACompileCopy1_0a278380> compiled.
Entity <rvi_test_vi_FPGACompileCopy1_0a278380> (Architecture <vhdl_labview>) compiled.
Compiling vhdl file "C:/NIFPGA85/srvrTmp/LOCALH~1/TEST_F~1/rvi_XDNodeRunTimeDep_lvlib_loadlvalarms46421008_180530708.vhd" in Library work.
Entity <rvi_XDNodeRunTimeDep_lvlib_loadlvalarms46421008_180530708> compiled.
Entity <rvi_XDNodeRunTimeDep_lvlib_loadlvalarms46421008_180530708> (Architecture <behavioral>) compiled.
Compiling vhdl file "C:/NIFPGA85/srvrTmp/LOCALH~1/TEST_F~1/XNode_h2c45410_n99e98cc_0aad9e10.vhd" in Library work.
Entity <XNode_h2c45410_n99e98cc_0aad9e10> compiled.
Entity <XNode_h2c45410_n99e98cc_0aad9e10> (Architecture <vhdl_labview>) compiled.
Compiling vhdl file "C:/NIFPGA85/srvrTmp/LOCALH~1/TEST_F~1/localResholderWresult_005f.vhd" in Library work.
Entity <localResholderWresult_005f> compiled.
Entity <localResholderWresult_005f> (Architecture <rtl>) compiled.
Compiling vhdl file "C:/NIFPGA85/srvrTmp/LOCALH~1/TEST_F~1/rvi_test_vi_FPGACompileCopy1.vhd" in Library work.
Entity <rvi_test_vi_FPGACompileCopy1> compiled.
Entity <rvi_test_vi_FPGACompileCopy1> (Architecture <vhdl_labview>) compiled.
Compiling vhdl file "C:/NIFPGA85/srvrTmp/LOCALH~1/TEST_F~1/toplevel_gen.vhd" in Library work.
Entity <toplevel_gen> compiled.
Entity <toplevel_gen> (Architecture <vhdl_modgen>) compiled.

=========================================================================
*                     Design Hierarchy Analysis                         *
=========================================================================
Analyzing hierarchy for entity <toplevel_gen> in library <work> (architecture <vhdl_modgen>).

Analyzing hierarchy for entity <rvi_test_vi_FPGACompileCopy1> in library <work> (architecture <vhdl_labview>).


Analyzing hierarchy for entity <XNode_h2c45410_n99e98cc_0aad9e10> in library <work> (architecture <vhdl_labview>).

Analyzing hierarchy for entity <rvi_test_vi_FPGACompileCopy1_0A278380> in library <work> (architecture <vhdl_labview>).


Analyzing hierarchy for entity <XNode_h2c45410_n99e944c_0ab3a308> in library <work> (architecture <vhdl_labview>).

Analyzing hierarchy for entity <prim_CVT_Fascade_02C45410_0AB39BD0> in library <work> (architecture <vhdl_labview>).

Analyzing hierarchy for entity <prim_CVT_Fascade_02C45410_09A2DC60> in library <work> (architecture <vhdl_labview>).
















Analyzing hierarchy for entity <rvi_XDNodeRunTimeDep_lvlib_loadlvalarms46421008_180530708> in library <work> (architecture <behavioral>).



Analyzing hierarchy for entity <XNode_h2c45410_n99e28cc_0acd9720> in library <work> (architecture <vhdl_labview>).

Analyzing hierarchy for entity <XNode_h2c45410_n99e954c_09a2e7f8> in library <work> (architecture <vhdl_labview>).


Analyzing hierarchy for entity <demux_Fascade_02C45410_0ABE80B4> in library <work> (architecture <vhdl_labview>).









Analyzing hierarchy for entity <MiteInterface> in library <work> (architecture <rtl>).











Analyzing hierarchy for entity <demux_Fascade_02C45410_0ACD5AF4> in library <work> (architecture <vhdl_labview>).





Analyzing hierarchy for entity <MiteInterfaceOutputEnables> in library <work> (architecture <rtl>).













=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing Entity <toplevel_gen> in library <work> (Architecture <vhdl_modgen>).
    Set user-defined property "OPTIMIZE =  off" for signal <Clk40> in unit <toplevel_gen>.
    Set user-defined property "OPTIMIZE =  off" for signal <temperature_miso>.
    Set user-defined property "OPTIMIZE =  off" for signal <FPGA_temperature_miso>.
    Set user-defined property "OPTIMIZE =  off" for signal <CPU_temperature_miso>.
    Set property "max_fanout = 1000000" for signal <aDiagramReset>.
WARNING:Xst:1994 - "C:/NIFPGA85/srvrTmp/LOCALH~1/TEST_F~1/PkgNiUtilities.vhd" line 235: Null range in type of signal <rval>.
WARNING:Xst:1995 - "C:/NIFPGA85/srvrTmp/LOCALH~1/TEST_F~1/PkgNiUtilities.vhd" line 237: Use of null array on signal <rval> is not supported.
WARNING:Xst:2211 - "C:/NIFPGA85/srvrTmp/LOCALH~1/TEST_F~1/PkgNiUtilities.vhd" line 1290: Instantiating black box module <BUFG>.
WARNING:Xst:753 - "C:/NIFPGA85/srvrTmp/LOCALH~1/TEST_F~1/PkgNiUtilities.vhd" line 1481: Unconnected output port 'iAutoReset' of component 'rvi_test_vi_FPGACompileCopy1'.
Entity <toplevel_gen> analyzed. Unit <toplevel_gen> generated.

Analyzing Entity <rvi_test_vi_FPGACompileCopy1> in library <work> (Architecture <vhdl_labview>).
Entity <rvi_test_vi_FPGACompileCopy1> analyzed. Unit <rvi_test_vi_FPGACompileCopy1> generated.

Analyzing generic Entity <localResholderWresult_005f> in library <work> (Architecture <rtl>).
Entity <localResholderWresult_005f> analyzed. Unit <localResholderWresult_005f> generated.

Analyzing Entity <XNode_h2c45410_n99e98cc_0aad9e10> in library <work> (Architecture <vhdl_labview>).
Entity <XNode_h2c45410_n99e98cc_0aad9e10> analyzed. Unit <XNode_h2c45410_n99e98cc_0aad9e10> generated.

Analyzing Entity <rvi_XDNodeRunTimeDep_lvlib_loadlvalarms46421008_180530708> in library <work> (Architecture <behavioral>).
Entity <rvi_XDNodeRunTimeDep_lvlib_loadlvalarms46421008_180530708> analyzed. Unit <rvi_XDNodeRunTimeDep_lvlib_loadlvalarms46421008_180530708> generated.

Analyzing Entity <rvi_test_vi_FPGACompileCopy1_0A278380> in library <work> (Architecture <vhdl_labview>).
WARNING:Xst:753 - "C:/NIFPGA85/srvrTmp/LOCALH~1/TEST_F~1/rvi_test_vi_FPGACompileCopy1_0a278380.vhd" line 232: Unconnected output port 't0acd59e0' of component 'XNode_h2c45410_n99e954c_09a2e7f8'.
Entity <rvi_test_vi_FPGACompileCopy1_0A278380> analyzed. Unit <rvi_test_vi_FPGACompileCopy1_0A278380> generated.

Analyzing generic Entity <scTunnel_0030> in library <work> (Architecture <rtl>).
Entity <scTunnel_0030> analyzed. Unit <scTunnel_0030> generated.

Analyzing generic Entity <cpdarith_0031> in library <work> (Architecture <vhdl_modgen>).
Entity <cpdarith_0031> analyzed. Unit <cpdarith_0031> generated.

Analyzing generic Entity <nirvi_ZeroDelayer> in library <work> (Architecture <rtl>).
Entity <nirvi_ZeroDelayer> analyzed. Unit <nirvi_ZeroDelayer> generated.

Analyzing generic Entity <prim_cparith_or0_0_0031> in library <work> (Architecture <rtl>).
Entity <prim_cparith_or0_0_0031> analyzed. Unit <prim_cparith_or0_0_0031> generated.

Analyzing generic Entity <prim_cparith_or0_1_0031> in library <work> (Architecture <rtl>).
Entity <prim_cparith_or0_1_0031> analyzed. Unit <prim_cparith_or0_1_0031> generated.

Analyzing generic Entity <prim_cparith_or0_2_0031> in library <work> (Architecture <rtl>).
Entity <prim_cparith_or0_2_0031> analyzed. Unit <prim_cparith_or0_2_0031> generated.

Analyzing generic Entity <prim_cparith_or0_3_0031> in library <work> (Architecture <rtl>).
Entity <prim_cparith_or0_3_0031> analyzed. Unit <prim_cparith_or0_3_0031> generated.

Analyzing generic Entity <prim_cparith_or1_0_0031> in library <work> (Architecture <rtl>).
Entity <prim_cparith_or1_0_0031> analyzed. Unit <prim_cparith_or1_0_0031> generated.

Analyzing generic Entity <prim_cparith_or1_1_0031> in library <work> (Architecture <rtl>).
Entity <prim_cparith_or1_1_0031> analyzed. Unit <prim_cparith_or1_1_0031> generated.

Analyzing generic Entity <prim_cparith_or2_0_0031> in library <work> (Architecture <rtl>).
Entity <prim_cparith_or2_0_0031> analyzed. Unit <prim_cparith_or2_0_0031> generated.

Analyzing generic Entity <prim_cparith_or3_0_0031> in library <work> (Architecture <rtl>).
Entity <prim_cparith_or3_0_0031> analyzed. Unit <prim_cparith_or3_0_0031> generated.

Analyzing Entity <XNode_h2c45410_n99e28cc_0acd9720> in library <work> (Architecture <vhdl_labview>).
WARNING:Xst:753 - "C:/NIFPGA85/srvrTmp/LOCALH~1/TEST_F~1/XNode_h2c45410_n99e28cc_0acd9720.vhd" line 67: Unconnected output port 'cluster_element_1' of component 'demux_Fascade_02C45410_0ACD5AF4'.
WARNING:Xst:753 - "C:/NIFPGA85/srvrTmp/LOCALH~1/TEST_F~1/XNode_h2c45410_n99e28cc_0acd9720.vhd" line 67: Unconnected output port 'cluster_element_2' of component 'demux_Fascade_02C45410_0ACD5AF4'.
WARNING:Xst:753 - "C:/NIFPGA85/srvrTmp/LOCALH~1/TEST_F~1/XNode_h2c45410_n99e28cc_0acd9720.vhd" line 67: Unconnected output port 'cluster_element_3' of component 'demux_Fascade_02C45410_0ACD5AF4'.
WARNING:Xst:753 - "C:/NIFPGA85/srvrTmp/LOCALH~1/TEST_F~1/XNode_h2c45410_n99e28cc_0acd9720.vhd" line 67: Unconnected output port 'cluster_element_4' of component 'demux_Fascade_02C45410_0ACD5AF4'.
WARNING:Xst:753 - "C:/NIFPGA85/srvrTmp/LOCALH~1/TEST_F~1/XNode_h2c45410_n99e28cc_0acd9720.vhd" line 67: Unconnected output port 'cluster_element_5' of component 'demux_Fascade_02C45410_0ACD5AF4'.
WARNING:Xst:753 - "C:/NIFPGA85/srvrTmp/LOCALH~1/TEST_F~1/XNode_h2c45410_n99e28cc_0acd9720.vhd" line 67: Unconnected output port 'cluster_element_6' of component 'demux_Fascade_02C45410_0ACD5AF4'.
WARNING:Xst:753 - "C:/NIFPGA85/srvrTmp/LOCALH~1/TEST_F~1/XNode_h2c45410_n99e28cc_0acd9720.vhd" line 67: Unconnected output port 'cluster_element_7' of component 'demux_Fascade_02C45410_0ACD5AF4'.
WARNING:Xst:753 - "C:/NIFPGA85/srvrTmp/LOCALH~1/TEST_F~1/XNode_h2c45410_n99e28cc_0acd9720.vhd" line 67: Unconnected output port 'cluster_element_8' of component 'demux_Fascade_02C45410_0ACD5AF4'.
WARNING:Xst:753 - "C:/NIFPGA85/srvrTmp/LOCALH~1/TEST_F~1/XNode_h2c45410_n99e28cc_0acd9720.vhd" line 67: Unconnected output port 'cluster_element_9' of component 'demux_Fascade_02C45410_0ACD5AF4'.
WARNING:Xst:753 - "C:/NIFPGA85/srvrTmp/LOCALH~1/TEST_F~1/XNode_h2c45410_n99e28cc_0acd9720.vhd" line 67: Unconnected output port 'cluster_element_10' of component 'demux_Fascade_02C45410_0ACD5AF4'.
WARNING:Xst:753 - "C:/NIFPGA85/srvrTmp/LOCALH~1/TEST_F~1/XNode_h2c45410_n99e28cc_0acd9720.vhd" line 67: Unconnected output port 'cluster_element_13' of component 'demux_Fascade_02C45410_0ACD5AF4'.
WARNING:Xst:753 - "C:/NIFPGA85/srvrTmp/LOCALH~1/TEST_F~1/XNode_h2c45410_n99e28cc_0acd9720.vhd" line 67: Unconnected output port 'cluster_element_14' of component 'demux_Fascade_02C45410_0ACD5AF4'.
WARNING:Xst:753 - "C:/NIFPGA85/srvrTmp/LOCALH~1/TEST_F~1/XNode_h2c45410_n99e28cc_0acd9720.vhd" line 67: Unconnected output port 'cluster_element_15' of component 'demux_Fascade_02C45410_0ACD5AF4'.
WARNING:Xst:753 - "C:/NIFPGA85/srvrTmp/LOCALH~1/TEST_F~1/XNode_h2c45410_n99e28cc_0acd9720.vhd" line 67: Unconnected output port 'cluster_element_16' of component 'demux_Fascade_02C45410_0ACD5AF4'.
WARNING:Xst:753 - "C:/NIFPGA85/srvrTmp/LOCALH~1/TEST_F~1/XNode_h2c45410_n99e28cc_0acd9720.vhd" line 67: Unconnected output port 'cluster_element_17' of component 'demux_Fascade_02C45410_0ACD5AF4'.
WARNING:Xst:753 - "C:/NIFPGA85/srvrTmp/LOCALH~1/TEST_F~1/XNode_h2c45410_n99e28cc_0acd9720.vhd" line 67: Unconnected output port 'cluster_element_18' of component 'demux_Fascade_02C45410_0ACD5AF4'.
WARNING:Xst:753 - "C:/NIFPGA85/srvrTmp/LOCALH~1/TEST_F~1/XNode_h2c45410_n99e28cc_0acd9720.vhd" line 67: Unconnected output port 'cluster_element_19' of component 'demux_Fascade_02C45410_0ACD5AF4'.
WARNING:Xst:753 - "C:/NIFPGA85/srvrTmp/LOCALH~1/TEST_F~1/XNode_h2c45410_n99e28cc_0acd9720.vhd" line 67: Unconnected output port 'cluster_element_20' of component 'demux_Fascade_02C45410_0ACD5AF4'.
WARNING:Xst:753 - "C:/NIFPGA85/srvrTmp/LOCALH~1/TEST_F~1/XNode_h2c45410_n99e28cc_0acd9720.vhd" line 67: Unconnected output port 'cluster_element_21' of component 'demux_Fascade_02C45410_0ACD5AF4'.
WARNING:Xst:753 - "C:/NIFPGA85/srvrTmp/LOCALH~1/TEST_F~1/XNode_h2c45410_n99e28cc_0acd9720.vhd" line 67: Unconnected output port 'cluster_element_24' of component 'demux_Fascade_02C45410_0ACD5AF4'.
WARNING:Xst:753 - "C:/NIFPGA85/srvrTmp/LOCALH~1/TEST_F~1/XNode_h2c45410_n99e28cc_0acd9720.vhd" line 67: Unconnected output port 'cluster_element_25' of component 'demux_Fascade_02C45410_0ACD5AF4'.
WARNING:Xst:753 - "C:/NIFPGA85/srvrTmp/LOCALH~1/TEST_F~1/XNode_h2c45410_n99e28cc_0acd9720.vhd" line 67: Unconnected output port 'cluster_element_26' of component 'demux_Fascade_02C45410_0ACD5AF4'.
WARNING:Xst:753 - "C:/NIFPGA85/srvrTmp/LOCALH~1/TEST_F~1/XNode_h2c45410_n99e28cc_0acd9720.vhd" line 67: Unconnected output port 'cluster_element_27' of component 'demux_Fascade_02C45410_0ACD5AF4'.
WARNING:Xst:753 - "C:/NIFPGA85/srvrTmp/LOCALH~1/TEST_F~1/XNode_h2c45410_n99e28cc_0acd9720.vhd" line 67: Unconnected output port 'cluster_element_28' of component 'demux_Fascade_02C45410_0ACD5AF4'.
Entity <XNode_h2c45410_n99e28cc_0acd9720> analyzed. Unit <XNode_h2c45410_n99e28cc_0acd9720> generated.

Analyzing Entity <demux_Fascade_02C45410_0ACD5AF4> in library <work> (Architecture <vhdl_labview>).
Entity <demux_Fascade_02C45410_0ACD5AF4> analyzed. Unit <demux_Fascade_02C45410_0ACD5AF4> generated.

Analyzing generic Entity <demux_001f> in library <work> (Architecture <vhdl_modgen>).
Entity <demux_001f> analyzed. Unit <demux_001f> generated.

Analyzing Entity <XNode_h2c45410_n99e954c_09a2e7f8> in library <work> (Architecture <vhdl_labview>).
Entity <XNode_h2c45410_n99e954c_09a2e7f8> analyzed. Unit <XNode_h2c45410_n99e954c_09a2e7f8> generated.

Analyzing generic Entity <timedLoop_0060> in library <work> (Architecture <rtl>).
Entity <timedLoop_0060> analyzed. Unit <timedLoop_0060> generated.

Analyzing generic Entity <TimedLoopController> in library <work> (Architecture <rtl>).
Entity <TimedLoopController> analyzed. Unit <TimedLoopController> generated.

Analyzing Entity <XNode_h2c45410_n99e944c_0ab3a308> in library <work> (Architecture <vhdl_labview>).
WARNING:Xst:753 - "C:/NIFPGA85/srvrTmp/LOCALH~1/TEST_F~1/XNode_h2c45410_n99e944c_0ab3a308.vhd" line 66: Unconnected output port 'cluster_element_1' of component 'demux_Fascade_02C45410_0ABE80B4'.
WARNING:Xst:753 - "C:/NIFPGA85/srvrTmp/LOCALH~1/TEST_F~1/XNode_h2c45410_n99e944c_0ab3a308.vhd" line 66: Unconnected output port 'cluster_element_2' of component 'demux_Fascade_02C45410_0ABE80B4'.
WARNING:Xst:753 - "C:/NIFPGA85/srvrTmp/LOCALH~1/TEST_F~1/XNode_h2c45410_n99e944c_0ab3a308.vhd" line 66: Unconnected output port 'cluster_element_3' of component 'demux_Fascade_02C45410_0ABE80B4'.
WARNING:Xst:753 - "C:/NIFPGA85/srvrTmp/LOCALH~1/TEST_F~1/XNode_h2c45410_n99e944c_0ab3a308.vhd" line 66: Unconnected output port 'cluster_element_4' of component 'demux_Fascade_02C45410_0ABE80B4'.
WARNING:Xst:753 - "C:/NIFPGA85/srvrTmp/LOCALH~1/TEST_F~1/XNode_h2c45410_n99e944c_0ab3a308.vhd" line 66: Unconnected output port 'cluster_element_5' of component 'demux_Fascade_02C45410_0ABE80B4'.
WARNING:Xst:753 - "C:/NIFPGA85/srvrTmp/LOCALH~1/TEST_F~1/XNode_h2c45410_n99e944c_0ab3a308.vhd" line 66: Unconnected output port 'cluster_element_6' of component 'demux_Fascade_02C45410_0ABE80B4'.
WARNING:Xst:753 - "C:/NIFPGA85/srvrTmp/LOCALH~1/TEST_F~1/XNode_h2c45410_n99e944c_0ab3a308.vhd" line 66: Unconnected output port 'cluster_element_7' of component 'demux_Fascade_02C45410_0ABE80B4'.
WARNING:Xst:753 - "C:/NIFPGA85/srvrTmp/LOCALH~1/TEST_F~1/XNode_h2c45410_n99e944c_0ab3a308.vhd" line 66: Unconnected output port 'cluster_element_8' of component 'demux_Fascade_02C45410_0ABE80B4'.
WARNING:Xst:753 - "C:/NIFPGA85/srvrTmp/LOCALH~1/TEST_F~1/XNode_h2c45410_n99e944c_0ab3a308.vhd" line 66: Unconnected output port 'cluster_element_9' of component 'demux_Fascade_02C45410_0ABE80B4'.
WARNING:Xst:753 - "C:/NIFPGA85/srvrTmp/LOCALH~1/TEST_F~1/XNode_h2c45410_n99e944c_0ab3a308.vhd" line 66: Unconnected output port 'cluster_element_10' of component 'demux_Fascade_02C45410_0ABE80B4'.
WARNING:Xst:753 - "C:/NIFPGA85/srvrTmp/LOCALH~1/TEST_F~1/XNode_h2c45410_n99e944c_0ab3a308.vhd" line 66: Unconnected output port 'cluster_element_13' of component 'demux_Fascade_02C45410_0ABE80B4'.
WARNING:Xst:753 - "C:/NIFPGA85/srvrTmp/LOCALH~1/TEST_F~1/XNode_h2c45410_n99e944c_0ab3a308.vhd" line 66: Unconnected output port 'cluster_element_14' of component 'demux_Fascade_02C45410_0ABE80B4'.
WARNING:Xst:753 - "C:/NIFPGA85/srvrTmp/LOCALH~1/TEST_F~1/XNode_h2c45410_n99e944c_0ab3a308.vhd" line 66: Unconnected output port 'cluster_element_15' of component 'demux_Fascade_02C45410_0ABE80B4'.
WARNING:Xst:753 - "C:/NIFPGA85/srvrTmp/LOCALH~1/TEST_F~1/XNode_h2c45410_n99e944c_0ab3a308.vhd" line 66: Unconnected output port 'cluster_element_16' of component 'demux_Fascade_02C45410_0ABE80B4'.
WARNING:Xst:753 - "C:/NIFPGA85/srvrTmp/LOCALH~1/TEST_F~1/XNode_h2c45410_n99e944c_0ab3a308.vhd" line 66: Unconnected output port 'cluster_element_17' of component 'demux_Fascade_02C45410_0ABE80B4'.
WARNING:Xst:753 - "C:/NIFPGA85/srvrTmp/LOCALH~1/TEST_F~1/XNode_h2c45410_n99e944c_0ab3a308.vhd" line 66: Unconnected output port 'cluster_element_18' of component 'demux_Fascade_02C45410_0ABE80B4'.
WARNING:Xst:753 - "C:/NIFPGA85/srvrTmp/LOCALH~1/TEST_F~1/XNode_h2c45410_n99e944c_0ab3a308.vhd" line 66: Unconnected output port 'cluster_element_19' of component 'demux_Fascade_02C45410_0ABE80B4'.
WARNING:Xst:753 - "C:/NIFPGA85/srvrTmp/LOCALH~1/TEST_F~1/XNode_h2c45410_n99e944c_0ab3a308.vhd" line 66: Unconnected output port 'cluster_element_20' of component 'demux_Fascade_02C45410_0ABE80B4'.
WARNING:Xst:753 - "C:/NIFPGA85/srvrTmp/LOCALH~1/TEST_F~1/XNode_h2c45410_n99e944c_0ab3a308.vhd" line 66: Unconnected output port 'cluster_element_21' of component 'demux_Fascade_02C45410_0ABE80B4'.
WARNING:Xst:753 - "C:/NIFPGA85/srvrTmp/LOCALH~1/TEST_F~1/XNode_h2c45410_n99e944c_0ab3a308.vhd" line 66: Unconnected output port 'cluster_element_24' of component 'demux_Fascade_02C45410_0ABE80B4'.
WARNING:Xst:753 - "C:/NIFPGA85/srvrTmp/LOCALH~1/TEST_F~1/XNode_h2c45410_n99e944c_0ab3a308.vhd" line 66: Unconnected output port 'cluster_element_25' of component 'demux_Fascade_02C45410_0ABE80B4'.
WARNING:Xst:753 - "C:/NIFPGA85/srvrTmp/LOCALH~1/TEST_F~1/XNode_h2c45410_n99e944c_0ab3a308.vhd" line 66: Unconnected output port 'cluster_element_26' of component 'demux_Fascade_02C45410_0ABE80B4'.
WARNING:Xst:753 - "C:/NIFPGA85/srvrTmp/LOCALH~1/TEST_F~1/XNode_h2c45410_n99e944c_0ab3a308.vhd" line 66: Unconnected output port 'cluster_element_27' of component 'demux_Fascade_02C45410_0ABE80B4'.
WARNING:Xst:753 - "C:/NIFPGA85/srvrTmp/LOCALH~1/TEST_F~1/XNode_h2c45410_n99e944c_0ab3a308.vhd" line 66: Unconnected output port 'cluster_element_28' of component 'demux_Fascade_02C45410_0ABE80B4'.
Entity <XNode_h2c45410_n99e944c_0ab3a308> analyzed. Unit <XNode_h2c45410_n99e944c_0ab3a308> generated.

Analyzing Entity <demux_Fascade_02C45410_0ABE80B4> in library <work> (Architecture <vhdl_labview>).
Entity <demux_Fascade_02C45410_0ABE80B4> analyzed. Unit <demux_Fascade_02C45410_0ABE80B4> generated.

Analyzing generic Entity <demux_003c> in library <work> (Architecture <vhdl_modgen>).
Entity <demux_003c> analyzed. Unit <demux_003c> generated.

Analyzing Entity <prim_CVT_Fascade_02C45410_0AB39BD0> in library <work> (Architecture <vhdl_labview>).
WARNING:Xst:753 - "C:/NIFPGA85/srvrTmp/LOCALH~1/TEST_F~1/prim_CVT_Fascade_02C45410_0ab39bd0.vhd" line 359: Unconnected output port 'cluster_type' of component 'mux_level1_forZ_0050'.
WARNING:Xst:753 - "C:/NIFPGA85/srvrTmp/LOCALH~1/TEST_F~1/prim_CVT_Fascade_02C45410_0ab39bd0.vhd" line 456: Unconnected output port 'cOverflow' of component 'NiLvFxpCoerce'.
WARNING:Xst:753 - "C:/NIFPGA85/srvrTmp/LOCALH~1/TEST_F~1/prim_CVT_Fascade_02C45410_0ab39bd0.vhd" line 480: Unconnected output port 'cOverflow' of component 'NiLvFxpCoerce'.
Entity <prim_CVT_Fascade_02C45410_0AB39BD0> analyzed. Unit <prim_CVT_Fascade_02C45410_0AB39BD0> generated.

Analyzing generic Entity <demux_level1_forX_004f> in library <work> (Architecture <vhdl_modgen>).
Entity <demux_level1_forX_004f> analyzed. Unit <demux_level1_forX_004f> generated.

Analyzing generic Entity <mux_level1_forZ_0050> in library <work> (Architecture <vhdl_modgen>).
Entity <mux_level1_forZ_0050> analyzed. Unit <mux_level1_forZ_0050> generated.

Analyzing generic Entity <NiLvFxpCoerce> in library <work> (Architecture <rtl>).
WARNING:Xst:1748 - "C:/NIFPGA85/srvrTmp/LOCALH~1/TEST_F~1/PkgFxpArithmetic.vhd" line 609: VHDL Assertion Statement with non constant condition is ignored.
Entity <NiLvFxpCoerce> analyzed. Unit <NiLvFxpCoerce> generated.

Analyzing generic Entity <NiLvFxpEnableHandler> in library <work> (Architecture <rtl>).
Entity <NiLvFxpEnableHandler> analyzed. Unit <NiLvFxpEnableHandler> generated.

Analyzing Entity <prim_CVT_Fascade_02C45410_09A2DC60> in library <work> (Architecture <vhdl_labview>).
WARNING:Xst:753 - "C:/NIFPGA85/srvrTmp/LOCALH~1/TEST_F~1/prim_CVT_Fascade_02C45410_09a2dc60.vhd" line 359: Unconnected output port 'cluster_type' of component 'mux_level1_forZ_005b'.
WARNING:Xst:753 - "C:/NIFPGA85/srvrTmp/LOCALH~1/TEST_F~1/prim_CVT_Fascade_02C45410_09a2dc60.vhd" line 456: Unconnected output port 'cOverflow' of component 'NiLvFxpCoerce'.
WARNING:Xst:753 - "C:/NIFPGA85/srvrTmp/LOCALH~1/TEST_F~1/prim_CVT_Fascade_02C45410_09a2dc60.vhd" line 480: Unconnected output port 'cOverflow' of component 'NiLvFxpCoerce'.
Entity <prim_CVT_Fascade_02C45410_09A2DC60> analyzed. Unit <prim_CVT_Fascade_02C45410_09A2DC60> generated.

Analyzing generic Entity <demux_level1_forX_005a> in library <work> (Architecture <vhdl_modgen>).
Entity <demux_level1_forX_005a> analyzed. Unit <demux_level1_forX_005a> generated.

Analyzing generic Entity <mux_level1_forZ_005b> in library <work> (Architecture <vhdl_modgen>).
Entity <mux_level1_forZ_005b> analyzed. Unit <mux_level1_forZ_005b> generated.

Analyzing generic Entity <InvisibleResholder> in library <work> (Architecture <rtl>).
Entity <InvisibleResholder> analyzed. Unit <InvisibleResholder> generated.

Analyzing generic Entity <bushold> in library <work> (Architecture <rtl>).
Entity <bushold> analyzed. Unit <bushold> generated.

Analyzing generic Entity <HandshakeSLV.1> in library <work> (Architecture <struct>).
WARNING:Xst:753 - "C:/NIFPGA85/srvrTmp/LOCALH~1/TEST_F~1/HandshakeSLV.vhd" line 59: Unconnected output port 'iStoredData' of component 'HandshakeBase'.
    Set property "equivalent_register_removal = no" for unit <HandshakeBase.1>.
WARNING:Xst:37 - Unknown property "syn_direct_enable".
WARNING:Xst:37 - Unknown property "syn_direct_enable".
Entity <HandshakeSLV.1> analyzed. Unit <HandshakeSLV.1> generated.

Analyzing generic Entity <HandshakeBase.1> in library <work> (Architecture <behavior>).
WARNING:Xst:37 - Unknown property "syn_direct_enable".
WARNING:Xst:37 - Unknown property "syn_direct_enable".
Entity <HandshakeBase.1> analyzed. Unit <HandshakeBase.1> generated.

Analyzing generic Entity <HandshakeSLV.2> in library <work> (Architecture <struct>).
WARNING:Xst:753 - "C:/NIFPGA85/srvrTmp/LOCALH~1/TEST_F~1/HandshakeSLV.vhd" line 59: Unconnected output port 'iStoredData' of component 'HandshakeBase'.
    Set property "equivalent_register_removal = no" for unit <HandshakeBase.2>.
WARNING:Xst:37 - Unknown property "syn_direct_enable".
WARNING:Xst:37 - Unknown property "syn_direct_enable".
Entity <HandshakeSLV.2> analyzed. Unit <HandshakeSLV.2> generated.

Analyzing generic Entity <HandshakeBase.2> in library <work> (Architecture <behavior>).
WARNING:Xst:37 - Unknown property "syn_direct_enable".
WARNING:Xst:37 - Unknown property "syn_direct_enable".
Entity <HandshakeBase.2> analyzed. Unit <HandshakeBase.2> generated.

Analyzing generic Entity <ShiftRegComp> in library <work> (Architecture <rtl>).
Entity <ShiftRegComp> analyzed. Unit <ShiftRegComp> generated.

Analyzing generic Entity <Interface> in library <work> (Architecture <rtl>).
Entity <Interface> analyzed. Unit <Interface> generated.

Analyzing Entity <MiteInterface> in library <work> (Architecture <rtl>).
Entity <MiteInterface> analyzed. Unit <MiteInterface> generated.

Analyzing Entity <MiteInterfaceOutputEnables> in library <work> (Architecture <rtl>).
Entity <MiteInterfaceOutputEnables> analyzed. Unit <MiteInterfaceOutputEnables> generated.

Analyzing generic Entity <RegisterAccess> in library <work> (Architecture <rtl>).
Entity <RegisterAccess> analyzed. Unit <RegisterAccess> generated.

Analyzing generic Entity <RegisterAccess32> in library <work> (Architecture <rtl>).
Entity <RegisterAccess32> analyzed. Unit <RegisterAccess32> generated.

Analyzing generic Entity <MiteDmaComponent.1> in library <work> (Architecture <rtl>).
Entity <MiteDmaComponent.1> analyzed. Unit <MiteDmaComponent.1> generated.

Analyzing generic Entity <MiteDmaComponent.2> in library <work> (Architecture <rtl>).
Entity <MiteDmaComponent.2> analyzed. Unit <MiteDmaComponent.2> generated.

Analyzing generic Entity <MiteDmaComponent.3> in library <work> (Architecture <rtl>).
Entity <MiteDmaComponent.3> analyzed. Unit <MiteDmaComponent.3> generated.

Analyzing generic Entity <MiteIrq> in library <work> (Architecture <rtl>).
WARNING:Xst:819 - "C:/NIFPGA85/srvrTmp/LOCALH~1/TEST_F~1/MiteIrq.vhd" line 150: The following signals are missing in the process sensitivity list:
   mIrqInt.
Entity <MiteIrq> analyzed. Unit <MiteIrq> generated.

Analyzing generic Entity <HandshakeSLV.3> in library <work> (Architecture <struct>).
WARNING:Xst:753 - "C:/NIFPGA85/srvrTmp/LOCALH~1/TEST_F~1/HandshakeSLV.vhd" line 59: Unconnected output port 'iStoredData' of component 'HandshakeBase'.
    Set property "equivalent_register_removal = no" for unit <HandshakeBase.3>.
WARNING:Xst:37 - Unknown property "syn_direct_enable".
WARNING:Xst:37 - Unknown property "syn_direct_enable".
Entity <HandshakeSLV.3> analyzed. Unit <HandshakeSLV.3> generated.

Analyzing generic Entity <HandshakeBase.3> in library <work> (Architecture <behavior>).
WARNING:Xst:37 - Unknown property "syn_direct_enable".
WARNING:Xst:37 - Unknown property "syn_direct_enable".
Entity <HandshakeBase.3> analyzed. Unit <HandshakeBase.3> generated.

Analyzing generic Entity <ViControl> in library <work> (Architecture <rtl>).
Entity <ViControl> analyzed. Unit <ViControl> generated.

Analyzing generic Entity <ViSignature> in library <work> (Architecture <rtl>).
Entity <ViSignature> analyzed. Unit <ViSignature> generated.

Analyzing generic Entity <testaviaFPGACompileCopy1result0> in library <work> (Architecture <rtl>).
WARNING:Xst:753 - "C:/NIFPGA85/srvrTmp/LOCALH~1/TEST_F~1/testaviaFPGACompileCopy1result0.vhd" line 199: Unconnected output port 'cFpgaDataEnable' of component 'TerminalRegister'.
WARNING:Xst:753 - "C:/NIFPGA85/srvrTmp/LOCALH~1/TEST_F~1/testaviaFPGACompileCopy1result0.vhd" line 199: Unconnected output port 'cFpgaDataOut' of component 'TerminalRegister'.
Entity <testaviaFPGACompileCopy1result0> analyzed. Unit <testaviaFPGACompileCopy1result0> generated.

Analyzing generic Entity <TerminalRegister> in library <work> (Architecture <rtl>).
Entity <TerminalRegister> analyzed. Unit <TerminalRegister> generated.

Analyzing generic Entity <arb_rw_0AFB6A90_0073> in library <work> (Architecture <rtl>).
Entity <arb_rw_0AFB6A90_0073> analyzed. Unit <arb_rw_0AFB6A90_0073> generated.

Analyzing generic Entity <arb_rw_0AE9A608_0074> in library <work> (Architecture <rtl>).
Entity <arb_rw_0AE9A608_0074> analyzed. Unit <arb_rw_0AE9A608_0074> generated.

Analyzing generic Entity <CustomArbForMiteIoLikePortOnResInterface> in library <work> (Architecture <rtl>).
Entity <CustomArbForMiteIoLikePortOnResInterface> analyzed. Unit <CustomArbForMiteIoLikePortOnResInterface> generated.

Analyzing generic Entity <arb_rw_0B0C5CC8_0075> in library <work> (Architecture <rtl>).
Entity <arb_rw_0B0C5CC8_0075> analyzed. Unit <arb_rw_0B0C5CC8_0075> generated.

Analyzing generic Entity <arb_rw_0B0CE1D0_0076> in library <work> (Architecture <rtl>).
Entity <arb_rw_0B0CE1D0_0076> analyzed. Unit <arb_rw_0B0CE1D0_0076> generated.

Analyzing generic Entity <arb_rw_0B0C1B48_0077> in library <work> (Architecture <rtl>).
Entity <arb_rw_0B0C1B48_0077> analyzed. Unit <arb_rw_0B0C1B48_0077> generated.

Analyzing generic Entity <arb_rw_0B0C3710_0078> in library <work> (Architecture <rtl>).
Entity <arb_rw_0B0C3710_0078> analyzed. Unit <arb_rw_0B0C3710_0078> generated.

Analyzing generic Entity <arb_rw_0B0CC8D8_0079> in library <work> (Architecture <rtl>).
Entity <arb_rw_0B0CC8D8_0079> analyzed. Unit <arb_rw_0B0CC8D8_0079> generated.

Analyzing generic Entity <arb_rw_0B0CD520_007a> in library <work> (Architecture <rtl>).
Entity <arb_rw_0B0CD520_007a> analyzed. Unit <arb_rw_0B0CD520_007a> generated.


=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Performing bidirectional port resolution...
INFO:Xst:2561 - Always blocking tristate driving signal <temp_miso> in unit <toplevel_gen> is removed.
INFO:Xst:2561 - Always blocking tristate driving signal <dio_00> in unit <toplevel_gen> is removed.
INFO:Xst:2561 - Always blocking tristate driving signal <dio_01> in unit <toplevel_gen> is removed.
INFO:Xst:2561 - Always blocking tristate driving signal <dio_02> in unit <toplevel_gen> is removed.
INFO:Xst:2561 - Always blocking tristate driving signal <dio_03> in unit <toplevel_gen> is removed.
INFO:Xst:2561 - Always blocking tristate driving signal <dio_04> in unit <toplevel_gen> is removed.
INFO:Xst:2561 - Always blocking tristate driving signal <dio_10> in unit <toplevel_gen> is removed.
INFO:Xst:2561 - Always blocking tristate driving signal <dio_05> in unit <toplevel_gen> is removed.
INFO:Xst:2561 - Always blocking tristate driving signal <dio_11> in unit <toplevel_gen> is removed.
INFO:Xst:2561 - Always blocking tristate driving signal <dio_06> in unit <toplevel_gen> is removed.
INFO:Xst:2561 - Always blocking tristate driving signal <dio_12> in unit <toplevel_gen> is removed.
INFO:Xst:2561 - Always blocking tristate driving signal <dio_07> in unit <toplevel_gen> is removed.
INFO:Xst:2561 - Always blocking tristate driving signal <dio_13> in unit <toplevel_gen> is removed.
INFO:Xst:2561 - Always blocking tristate driving signal <dio_08> in unit <toplevel_gen> is removed.
INFO:Xst:2561 - Always blocking tristate driving signal <dio_14> in unit <toplevel_gen> is removed.
INFO:Xst:2561 - Always blocking tristate driving signal <dio_09> in unit <toplevel_gen> is removed.
INFO:Xst:2561 - Always blocking tristate driving signal <dio_20> in unit <toplevel_gen> is removed.
INFO:Xst:2561 - Always blocking tristate driving signal <dio_15> in unit <toplevel_gen> is removed.
INFO:Xst:2561 - Always blocking tristate driving signal <dio_21> in unit <toplevel_gen> is removed.
INFO:Xst:2561 - Always blocking tristate driving signal <dio_16> in unit <toplevel_gen> is removed.
INFO:Xst:2561 - Always blocking tristate driving signal <dio_22> in unit <toplevel_gen> is removed.
INFO:Xst:2561 - Always blocking tristate driving signal <dio_17> in unit <toplevel_gen> is removed.
INFO:Xst:2561 - Always blocking tristate driving signal <dio_23> in unit <toplevel_gen> is removed.
INFO:Xst:2561 - Always blocking tristate driving signal <dio_18> in unit <toplevel_gen> is removed.
INFO:Xst:2561 - Always blocking tristate driving signal <dio_24> in unit <toplevel_gen> is removed.
INFO:Xst:2561 - Always blocking tristate driving signal <dio_19> in unit <toplevel_gen> is removed.
INFO:Xst:2561 - Always blocking tristate driving signal <dio_30> in unit <toplevel_gen> is removed.
INFO:Xst:2561 - Always blocking tristate driving signal <dio_25> in unit <toplevel_gen> is removed.
INFO:Xst:2561 - Always blocking tristate driving signal <dio_31> in unit <toplevel_gen> is removed.
INFO:Xst:2561 - Always blocking tristate driving signal <dio_26> in unit <toplevel_gen> is removed.
INFO:Xst:2561 - Always blocking tristate driving signal <dio_32> in unit <toplevel_gen> is removed.
INFO:Xst:2561 - Always blocking tristate driving signal <dio_27> in unit <toplevel_gen> is removed.
INFO:Xst:2561 - Always blocking tristate driving signal <dio_33> in unit <toplevel_gen> is removed.
INFO:Xst:2561 - Always blocking tristate driving signal <dio_28> in unit <toplevel_gen> is removed.
INFO:Xst:2561 - Always blocking tristate driving signal <dio_34> in unit <toplevel_gen> is removed.
INFO:Xst:2561 - Always blocking tristate driving signal <dio_29> in unit <toplevel_gen> is removed.
INFO:Xst:2561 - Always blocking tristate driving signal <dio_40> in unit <toplevel_gen> is removed.
INFO:Xst:2561 - Always blocking tristate driving signal <dio_35> in unit <toplevel_gen> is removed.
INFO:Xst:2561 - Always blocking tristate driving signal <dio_41> in unit <toplevel_gen> is removed.
INFO:Xst:2561 - Always blocking tristate driving signal <dio_36> in unit <toplevel_gen> is removed.
INFO:Xst:2561 - Always blocking tristate driving signal <dio_42> in unit <toplevel_gen> is removed.
INFO:Xst:2561 - Always blocking tristate driving signal <dio_37> in unit <toplevel_gen> is removed.
INFO:Xst:2561 - Always blocking tristate driving signal <dio_43> in unit <toplevel_gen> is removed.
INFO:Xst:2561 - Always blocking tristate driving signal <dio_38> in unit <toplevel_gen> is removed.
INFO:Xst:2561 - Always blocking tristate driving signal <dio_44> in unit <toplevel_gen> is removed.
INFO:Xst:2561 - Always blocking tristate driving signal <dio_39> in unit <toplevel_gen> is removed.
INFO:Xst:2561 - Always blocking tristate driving signal <dio_50> in unit <toplevel_gen> is removed.
INFO:Xst:2561 - Always blocking tristate driving signal <dio_45> in unit <toplevel_gen> is removed.
INFO:Xst:2561 - Always blocking tristate driving signal <dio_51> in unit <toplevel_gen> is removed.
INFO:Xst:2561 - Always blocking tristate driving signal <dio_46> in unit <toplevel_gen> is removed.
INFO:Xst:2561 - Always blocking tristate driving signal <dio_52> in unit <toplevel_gen> is removed.
INFO:Xst:2561 - Always blocking tristate driving signal <dio_47> in unit <toplevel_gen> is removed.
INFO:Xst:2561 - Always blocking tristate driving signal <dio_53> in unit <toplevel_gen> is removed.
INFO:Xst:2561 - Always blocking tristate driving signal <dio_48> in unit <toplevel_gen> is removed.
INFO:Xst:2561 - Always blocking tristate driving signal <dio_54> in unit <toplevel_gen> is removed.
INFO:Xst:2561 - Always blocking tristate driving signal <dio_49> in unit <toplevel_gen> is removed.
INFO:Xst:2561 - Always blocking tristate driving signal <dio_60> in unit <toplevel_gen> is removed.
INFO:Xst:2561 - Always blocking tristate driving signal <dio_55> in unit <toplevel_gen> is removed.
INFO:Xst:2561 - Always blocking tristate driving signal <dio_61> in unit <toplevel_gen> is removed.
INFO:Xst:2561 - Always blocking tristate driving signal <dio_56> in unit <toplevel_gen> is removed.
INFO:Xst:2561 - Always blocking tristate driving signal <dio_62> in unit <toplevel_gen> is removed.
INFO:Xst:2561 - Always blocking tristate driving signal <dio_57> in unit <toplevel_gen> is removed.
INFO:Xst:2561 - Always blocking tristate driving signal <dio_63> in unit <toplevel_gen> is removed.
INFO:Xst:2561 - Always blocking tristate driving signal <dio_58> in unit <toplevel_gen> is removed.
INFO:Xst:2561 - Always blocking tristate driving signal <dio_64> in unit <toplevel_gen> is removed.
INFO:Xst:2561 - Always blocking tristate driving signal <dio_59> in unit <toplevel_gen> is removed.
INFO:Xst:2561 - Always blocking tristate driving signal <dio_70> in unit <toplevel_gen> is removed.
INFO:Xst:2561 - Always blocking tristate driving signal <dio_65> in unit <toplevel_gen> is removed.
INFO:Xst:2561 - Always blocking tristate driving signal <dio_71> in unit <toplevel_gen> is removed.
INFO:Xst:2561 - Always blocking tristate driving signal <dio_66> in unit <toplevel_gen> is removed.
INFO:Xst:2561 - Always blocking tristate driving signal <dio_72> in unit <toplevel_gen> is removed.
INFO:Xst:2561 - Always blocking tristate driving signal <dio_67> in unit <toplevel_gen> is removed.
INFO:Xst:2561 - Always blocking tristate driving signal <dio_73> in unit <toplevel_gen> is removed.
INFO:Xst:2561 - Always blocking tristate driving signal <dio_68> in unit <toplevel_gen> is removed.
INFO:Xst:2561 - Always blocking tristate driving signal <dio_74> in unit <toplevel_gen> is removed.
INFO:Xst:2561 - Always blocking tristate driving signal <dio_69> in unit <toplevel_gen> is removed.
INFO:Xst:2561 - Always blocking tristate driving signal <dio_75> in unit <toplevel_gen> is removed.
INFO:Xst:2561 - Always blocking tristate driving signal <dio_76> in unit <toplevel_gen> is removed.
INFO:Xst:2561 - Always blocking tristate driving signal <dio_77> in unit <toplevel_gen> is removed.
INFO:Xst:2561 - Always blocking tristate driving signal <dio_78> in unit <toplevel_gen> is removed.
INFO:Xst:2561 - Always blocking tristate driving signal <dio_79> in unit <toplevel_gen> is removed.
INFO:Xst:2561 - Always blocking tristate driving signal <configd> in unit <toplevel_gen> is removed.

Synthesizing Unit <localResholderWresult_005f>.
    Related source file is "C:/NIFPGA85/srvrTmp/LOCALH~1/TEST_F~1/localResholderWresult_005f.vhd".
    Found 1-bit register for signal <enable_out>.
    Summary:
	inferred   1 D-type flip-flop(s).
Unit <localResholderWresult_005f> synthesized.


Synthesizing Unit <InvisibleResholder>.
    Related source file is "C:/NIFPGA85/srvrTmp/LOCALH~1/TEST_F~1/InvisibleResholder.vhd".
WARNING:Xst:647 - Input <FromResbusholddummy<0>> is never used.
WARNING:Xst:1305 - Output <ToResbusholddummy> is never assigned. Tied to value 00.
    Found 1-bit register for signal <toggler>.
    Summary:
	inferred   1 D-type flip-flop(s).
Unit <InvisibleResholder> synthesized.


Synthesizing Unit <ViControl>.
    Related source file is "C:/NIFPGA85/srvrTmp/LOCALH~1/TEST_F~1/ViControl.vhd".
WARNING:Xst:647 - Input <interfaceClockHostReadFromReshold<1>> is never used.
WARNING:Xst:647 - Input <interfaceClockHostWriteFromReshold<1>> is never used.
WARNING:Xst:646 - Signal <iHostDataIn<31:3>> is assigned but never used.
WARNING:Xst:646 - Signal <iHostDataIn<0>> is assigned but never used.
    Found 1-bit register for signal <tDiagramEnableIn>.
    Found 1-bit register for signal <tDiagramEnableClear>.
    Found 1-bit register for signal <iDelayedHostRead<0>>.
    Found 1-bit register for signal <iDiagramEnableOut_ms>.
    Found 1-bit register for signal <iEnableClear>.
    Found 1-bit register for signal <iEnableIn>.
    Found 1-bit register for signal <iEnableOut>.
    Found 1-bit register for signal <iTimeoutBit>.
    Found 1-bit register for signal <tDiagramEnableClear_ms>.
    Found 1-bit register for signal <tDiagramEnableIn_ms>.
    Summary:
	inferred  10 D-type flip-flop(s).
Unit <ViControl> synthesized.


Synthesizing Unit <ViSignature>.
    Related source file is "C:/NIFPGA85/srvrTmp/LOCALH~1/TEST_F~1/ViSignature.vhd".
WARNING:Xst:647 - Input <Clk> is never used.
WARNING:Xst:647 - Input <clkHostReadFromReshold<1>> is never used.
WARNING:Xst:647 - Input <reset> is never used.
Unit <ViSignature> synthesized.


Synthesizing Unit <CustomArbForMiteIoLikePortOnResInterface>.
    Related source file is "C:/NIFPGA85/srvrTmp/LOCALH~1/TEST_F~1/CustomArbForMiteIoLikePortOnResInterface.vhd".
WARNING:Xst:647 - Input <Clk> is never used.
WARNING:Xst:647 - Input <reset> is never used.
WARNING:Xst:646 - Signal <interfaceClockRegPortIn.Data> is assigned but never used.
WARNING:Xst:646 - Signal <interfaceClockRegPortIn.Address> is assigned but never used.
WARNING:Xst:646 - Signal <interfaceClockRegPortIn.Rd<0>> is assigned but never used.
WARNING:Xst:646 - Signal <interfaceClockRegPortIn.Wt<0>> is assigned but never used.
Unit <CustomArbForMiteIoLikePortOnResInterface> synthesized.


Synthesizing Unit <rvi_XDNodeRunTimeDep_lvlib_loadlvalarms46421008_180530708>.
    Related source file is "C:/NIFPGA85/srvrTmp/LOCALH~1/TEST_F~1/rvi_XDNodeRunTimeDep_lvlib_loadlvalarms46421008_180530708.vhd".
WARNING:Xst:647 - Input <clk> is never used.
WARNING:Xst:647 - Input <enable_clr> is never used.
WARNING:Xst:647 - Input <reset> is never used.
Unit <rvi_XDNodeRunTimeDep_lvlib_loadlvalarms46421008_180530708> synthesized.


Synthesizing Unit <scTunnel_0030>.
    Related source file is "C:/NIFPGA85/srvrTmp/LOCALH~1/TEST_F~1/scTunnel_0030.vhd".
WARNING:Xst:647 - Input <enable_clr> is never used.
    Found 1-bit register for signal <dataOut<0>>.
    Summary:
	inferred   1 D-type flip-flop(s).
Unit <scTunnel_0030> synthesized.


Synthesizing Unit <XNode_h2c45410_n99e954c_09a2e7f8>.
    Related source file is "C:/NIFPGA85/srvrTmp/LOCALH~1/TEST_F~1/XNode_h2c45410_n99e954c_09a2e7f8.vhd".
WARNING:Xst:647 - Input <enable_clr> is never used.
WARNING:Xst:647 - Input <reset> is never used.
Unit <XNode_h2c45410_n99e954c_09a2e7f8> synthesized.


Synthesizing Unit <nirvi_ZeroDelayer>.
    Related source file is "C:/NIFPGA85/srvrTmp/LOCALH~1/TEST_F~1/nirvi_ZeroDelayer.vhd".
WARNING:Xst:647 - Input <clk> is never used.
WARNING:Xst:647 - Input <reset> is never used.
WARNING:Xst:647 - Input <syncReset> is never used.
Unit <nirvi_ZeroDelayer> synthesized.


Synthesizing Unit <prim_cparith_or0_0_0031>.
    Related source file is "C:/NIFPGA85/srvrTmp/LOCALH~1/TEST_F~1/prim_cparith_or0_0_0031.vhd".
WARNING:Xst:647 - Input <clk> is never used.
WARNING:Xst:647 - Input <reset> is never used.
Unit <prim_cparith_or0_0_0031> synthesized.


Synthesizing Unit <prim_cparith_or0_1_0031>.
    Related source file is "C:/NIFPGA85/srvrTmp/LOCALH~1/TEST_F~1/prim_cparith_or0_1_0031.vhd".
WARNING:Xst:647 - Input <clk> is never used.
WARNING:Xst:647 - Input <reset> is never used.
Unit <prim_cparith_or0_1_0031> synthesized.


Synthesizing Unit <prim_cparith_or0_2_0031>.
    Related source file is "C:/NIFPGA85/srvrTmp/LOCALH~1/TEST_F~1/prim_cparith_or0_2_0031.vhd".
WARNING:Xst:647 - Input <clk> is never used.
WARNING:Xst:647 - Input <reset> is never used.
Unit <prim_cparith_or0_2_0031> synthesized.


Synthesizing Unit <prim_cparith_or0_3_0031>.
    Related source file is "C:/NIFPGA85/srvrTmp/LOCALH~1/TEST_F~1/prim_cparith_or0_3_0031.vhd".
WARNING:Xst:647 - Input <clk> is never used.
WARNING:Xst:647 - Input <reset> is never used.
Unit <prim_cparith_or0_3_0031> synthesized.


Synthesizing Unit <prim_cparith_or1_0_0031>.
    Related source file is "C:/NIFPGA85/srvrTmp/LOCALH~1/TEST_F~1/prim_cparith_or1_0_0031.vhd".
WARNING:Xst:647 - Input <clk> is never used.
WARNING:Xst:647 - Input <reset> is never used.
Unit <prim_cparith_or1_0_0031> synthesized.


Synthesizing Unit <prim_cparith_or1_1_0031>.
    Related source file is "C:/NIFPGA85/srvrTmp/LOCALH~1/TEST_F~1/prim_cparith_or1_1_0031.vhd".
WARNING:Xst:647 - Input <clk> is never used.
WARNING:Xst:647 - Input <reset> is never used.
Unit <prim_cparith_or1_1_0031> synthesized.


Synthesizing Unit <prim_cparith_or2_0_0031>.
    Related source file is "C:/NIFPGA85/srvrTmp/LOCALH~1/TEST_F~1/prim_cparith_or2_0_0031.vhd".
WARNING:Xst:647 - Input <clk> is never used.
WARNING:Xst:647 - Input <reset> is never used.
Unit <prim_cparith_or2_0_0031> synthesized.


Synthesizing Unit <prim_cparith_or3_0_0031>.
    Related source file is "C:/NIFPGA85/srvrTmp/LOCALH~1/TEST_F~1/prim_cparith_or3_0_0031.vhd".
WARNING:Xst:647 - Input <clk> is never used.
WARNING:Xst:647 - Input <reset> is never used.
Unit <prim_cparith_or3_0_0031> synthesized.


Synthesizing Unit <demux_001f>.
    Related source file is "C:/NIFPGA85/srvrTmp/LOCALH~1/TEST_F~1/demux_001f.vhd".
WARNING:Xst:647 - Input <Clk> is never used.
WARNING:Xst:647 - Input <enable_clr> is never used.
WARNING:Xst:647 - Input <reset> is never used.
Unit <demux_001f> synthesized.


Synthesizing Unit <TimedLoopController>.
    Related source file is "C:/NIFPGA85/srvrTmp/LOCALH~1/TEST_F~1/TimedLoopController.vhd".
WARNING:Xst:1780 - Signal <iLpIteration> is never used or assigned.
    Found 1-bit register for signal <iLEnableOut<0>>.
    Summary:
	inferred   1 D-type flip-flop(s).
Unit <TimedLoopController> synthesized.


Synthesizing Unit <demux_003c>.
    Related source file is "C:/NIFPGA85/srvrTmp/LOCALH~1/TEST_F~1/demux_003c.vhd".
WARNING:Xst:647 - Input <Clk> is never used.
WARNING:Xst:647 - Input <enable_clr> is never used.
WARNING:Xst:647 - Input <reset> is never used.
Unit <demux_003c> synthesized.


Synthesizing Unit <demux_level1_forX_004f>.
    Related source file is "C:/NIFPGA85/srvrTmp/LOCALH~1/TEST_F~1/demux_level1_forX_004f.vhd".
WARNING:Xst:647 - Input <Clk> is never used.
WARNING:Xst:647 - Input <enable_clr> is never used.
WARNING:Xst:647 - Input <reset> is never used.
Unit <demux_level1_forX_004f> synthesized.


Synthesizing Unit <mux_level1_forZ_0050>.
    Related source file is "C:/NIFPGA85/srvrTmp/LOCALH~1/TEST_F~1/mux_level1_forZ_0050.vhd".
WARNING:Xst:647 - Input <Clk> is never used.
WARNING:Xst:647 - Input <enable_clr> is never used.
WARNING:Xst:647 - Input <reset> is never used.
WARNING:Xst:1305 - Output <cluster_type> is never assigned. Tied to value
   0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
   000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000.
Unit <mux_level1_forZ_0050> synthesized.


Synthesizing Unit <NiLvFxpEnableHandler>.
    Related source file is "C:/NIFPGA85/srvrTmp/LOCALH~1/TEST_F~1/NiLvFxpEnableHandler.vhd".
WARNING:Xst:647 - Input <Clk> is never used.
WARNING:Xst:647 - Input <aReset> is never used.
Unit <NiLvFxpEnableHandler> synthesized.


Synthesizing Unit <demux_level1_forX_005a>.
    Related source file is "C:/NIFPGA85/srvrTmp/LOCALH~1/TEST_F~1/demux_level1_forX_005a.vhd".
WARNING:Xst:647 - Input <Clk> is never used.
WARNING:Xst:647 - Input <enable_clr> is never used.
WARNING:Xst:647 - Input <reset> is never used.
Unit <demux_level1_forX_005a> synthesized.


Synthesizing Unit <mux_level1_forZ_005b>.
    Related source file is "C:/NIFPGA85/srvrTmp/LOCALH~1/TEST_F~1/mux_level1_forZ_005b.vhd".
WARNING:Xst:647 - Input <Clk> is never used.
WARNING:Xst:647 - Input <enable_clr> is never used.
WARNING:Xst:647 - Input <reset> is never used.
WARNING:Xst:1305 - Output <cluster_type> is never assigned. Tied to value
   0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
   000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000.
Unit <mux_level1_forZ_005b> synthesized.


Synthesizing Unit <ShiftRegComp>.
    Related source file is "C:/NIFPGA85/srvrTmp/LOCALH~1/TEST_F~1/ShiftRegComp.vhd".
    Found 1-bit register for signal <cRegRead<0>>.
    Found 4-bit down counter for signal <cCounter>.
    Found 1-bit register for signal <cDelayedWritePulse1<0>>.
    Found 1-bit register for signal <cDelayedWritePulse2<0>>.
    Found 1-bit register for signal <cReadShift<0>>.
    Found 96-bit register for signal <cShiftReg>.
    Summary:
	inferred   1 Counter(s).
	inferred 100 D-type flip-flop(s).
Unit <ShiftRegComp> synthesized.


Synthesizing Unit <HandshakeBase_1>.
    Related source file is "C:/NIFPGA85/srvrTmp/LOCALH~1/TEST_F~1/HandshakeBase.vhd".
WARNING:Xst:646 - Signal <oDlyDataAck<0>> is assigned but never used.
    Found 1-bit register for signal <oDataValid<0>>.
    Found 35-bit register for signal <oData>.
    Found 1-bit register for signal <iDlyPush<0>>.
    Found 1-bit register for signal <iLclReady<0>>.
    Found 1-bit xor2 for signal <iLclReady_0$xor0000> created at line 226.
    Found 35-bit register for signal <iLclStoredData>.
    Found 1-bit register for signal <iPushToggle<0>>.
    Found 1-bit register for signal <iRdyPushToggle<0>>.
    Found 1-bit register for signal <iRdyPushToggle_ms<0>>.
    Found 1-bit register for signal <iReset<0>>.
    Found 1-bit register for signal <iReset_ms<0>>.
    Found 1-bit register for signal <oDataAckRisingEdge<0>>.
    Found 1-bit register for signal <oDlyPushToggleChanged<0>>.
    Found 1-bit register for signal <oPushToggle0_ms<0>>.
    Found 1-bit register for signal <oPushToggle1<0>>.
    Found 1-bit register for signal <oPushToggle2<0>>.
    Found 1-bit xor2 for signal <oPushToggleChanged<0>>.
    Found 1-bit register for signal <oPushToggleChangeStored<0>>.
    Found 1-bit register for signal <oPushToggleToReady<0>>.
    Summary:
	inferred  85 D-type flip-flop(s).
Unit <HandshakeBase_1> synthesized.


Synthesizing Unit <HandshakeBase_2>.
    Related source file is "C:/NIFPGA85/srvrTmp/LOCALH~1/TEST_F~1/HandshakeBase.vhd".
WARNING:Xst:646 - Signal <oDlyDataAck<0>> is assigned but never used.
    Found 1-bit register for signal <oDataValid<0>>.
    Found 32-bit register for signal <oData>.
    Found 1-bit register for signal <iDlyPush<0>>.
    Found 1-bit register for signal <iLclReady<0>>.
    Found 1-bit xor2 for signal <iLclReady_0$xor0000> created at line 226.
    Found 32-bit register for signal <iLclStoredData>.
    Found 1-bit register for signal <iPushToggle<0>>.
    Found 1-bit register for signal <iRdyPushToggle<0>>.
    Found 1-bit register for signal <iRdyPushToggle_ms<0>>.
    Found 1-bit register for signal <iReset<0>>.
    Found 1-bit register for signal <iReset_ms<0>>.
    Found 1-bit register for signal <oDataAckRisingEdge<0>>.
    Found 1-bit register for signal <oDlyPushToggleChanged<0>>.
    Found 1-bit register for signal <oPushToggle0_ms<0>>.
    Found 1-bit register for signal <oPushToggle1<0>>.
    Found 1-bit register for signal <oPushToggle2<0>>.
    Found 1-bit xor2 for signal <oPushToggleChanged<0>>.
    Found 1-bit register for signal <oPushToggleChangeStored<0>>.
    Found 1-bit register for signal <oPushToggleToReady<0>>.
    Summary:
	inferred  79 D-type flip-flop(s).
Unit <HandshakeBase_2> synthesized.


Synthesizing Unit <MiteInterfaceOutputEnables>.
    Related source file is "C:/NIFPGA85/srvrTmp/LOCALH~1/TEST_F~1/MiteInterfaceOutputEnables.vhd".
    Found finite state machine <FSM_0> for signal <mAccessType>.
    -----------------------------------------------------------------------
    | States             | 4                                              |
    | Transitions        | 9                                              |
    | Inputs             | 3                                              |
    | Outputs            | 1                                              |
    | Clock              | MiteClk (rising_edge)                          |
    | Reset              | aMiteReset<0> (positive)                       |
    | Reset type         | asynchronous                                   |
    | Reset State        | notreading                                     |
    | Power Up State     | dmaread                                        |
    | Encoding           | automatic                                      |
    | Implementation     | automatic                                      |
    -----------------------------------------------------------------------
    Found finite state machine <FSM_1> for signal <mAccessType0>.
    -----------------------------------------------------------------------
    | States             | 3                                              |
    | Transitions        | 9                                              |
    | Inputs             | 2                                              |
    | Outputs            | 1                                              |
    | Clock              | MiteClk (rising_edge)                          |
    | Reset              | aMiteReset<0> (positive)                       |
    | Reset type         | asynchronous                                   |
    | Reset State        | noaccess                                       |
    | Power Up State     | dma                                            |
    | Encoding           | automatic                                      |
    | Implementation     | automatic                                      |
    -----------------------------------------------------------------------
    Found 1-bit register for signal <mIoReadyOE>.
    Found 1-bit register for signal <mDataOE>.
    Summary:
	inferred   2 Finite State Machine(s).
	inferred   2 D-type flip-flop(s).
Unit <MiteInterfaceOutputEnables> synthesized.


Synthesizing Unit <MiteDmaComponent_1>.
    Related source file is "C:/NIFPGA85/srvrTmp/LOCALH~1/TEST_F~1/MiteDmaComponent.vhd".
WARNING:Xst:647 - Input <mIoRegisterRd_n> is never used.
WARNING:Xst:647 - Input <BrdClk> is never used.
WARNING:Xst:647 - Input <bEnableClear> is never used.
WARNING:Xst:647 - Input <mIoRegisterWt_n> is never used.
WARNING:Xst:647 - Input <mIoRd_n> is never used.
WARNING:Xst:647 - Input <mIoDataIn> is never used.
WARNING:Xst:647 - Input <MiteClk> is never used.
WARNING:Xst:647 - Input <aReset<0>> is never used.
WARNING:Xst:647 - Input <bEnableIn> is never used.
WARNING:Xst:647 - Input <mIoWt_n> is never used.
WARNING:Xst:647 - Input <mIoAddr> is never used.
WARNING:Xst:647 - Input <bTimeout> is never used.
WARNING:Xst:647 - Input <mIoRegisterDataIn> is never used.
WARNING:Xst:647 - Input <mIoDevSel_n> is never used.
WARNING:Xst:647 - Input <mDmaAck_n> is never used.
WARNING:Xst:647 - Input <bDataIn> is never used.
WARNING:Xst:1780 - Signal <bResetForFifo> is never used or assigned.
WARNING:Xst:1780 - Signal <mResetDone> is never used or assigned.
WARNING:Xst:1780 - Signal <mResetForFifo> is never used or assigned.
WARNING:Xst:1780 - Signal <bDisable> is never used or assigned.
WARNING:Xst:1780 - Signal <bDataOutFromFifo> is never used or assigned.
WARNING:Xst:1780 - Signal <bEnableOutLoc> is never used or assigned.
WARNING:Xst:1780 - Signal <bPushPop> is never used or assigned.
WARNING:Xst:1780 - Signal <bFlagFromFifo> is never used or assigned.
WARNING:Xst:1780 - Signal <mResetBitFromRegister> is never used or assigned.
Unit <MiteDmaComponent_1> synthesized.


Synthesizing Unit <MiteDmaComponent_2>.
    Related source file is "C:/NIFPGA85/srvrTmp/LOCALH~1/TEST_F~1/MiteDmaComponent.vhd".
WARNING:Xst:647 - Input <mIoRegisterRd_n> is never used.
WARNING:Xst:647 - Input <BrdClk> is never used.
WARNING:Xst:647 - Input <bEnableClear> is never used.
WARNING:Xst:647 - Input <mIoRegisterWt_n> is never used.
WARNING:Xst:647 - Input <mIoRd_n> is never used.
WARNING:Xst:647 - Input <mIoDataIn> is never used.
WARNING:Xst:647 - Input <MiteClk> is never used.
WARNING:Xst:647 - Input <aReset<0>> is never used.
WARNING:Xst:647 - Input <bEnableIn> is never used.
WARNING:Xst:647 - Input <mIoWt_n> is never used.
WARNING:Xst:647 - Input <mIoAddr> is never used.
WARNING:Xst:647 - Input <bTimeout> is never used.
WARNING:Xst:647 - Input <mIoRegisterDataIn> is never used.
WARNING:Xst:647 - Input <mIoDevSel_n> is never used.
WARNING:Xst:647 - Input <mDmaAck_n> is never used.
WARNING:Xst:647 - Input <bDataIn> is never used.
WARNING:Xst:1780 - Signal <bResetForFifo> is never used or assigned.
WARNING:Xst:1780 - Signal <mResetDone> is never used or assigned.
WARNING:Xst:1780 - Signal <mResetForFifo> is never used or assigned.
WARNING:Xst:1780 - Signal <bDisable> is never used or assigned.
WARNING:Xst:1780 - Signal <bDataOutFromFifo> is never used or assigned.
WARNING:Xst:1780 - Signal <bEnableOutLoc> is never used or assigned.
WARNING:Xst:1780 - Signal <bPushPop> is never used or assigned.
WARNING:Xst:1780 - Signal <bFlagFromFifo> is never used or assigned.
WARNING:Xst:1780 - Signal <mResetBitFromRegister> is never used or assigned.
Unit <MiteDmaComponent_2> synthesized.


Synthesizing Unit <MiteDmaComponent_3>.
    Related source file is "C:/NIFPGA85/srvrTmp/LOCALH~1/TEST_F~1/MiteDmaComponent.vhd".
WARNING:Xst:647 - Input <mIoRegisterRd_n> is never used.
WARNING:Xst:647 - Input <BrdClk> is never used.
WARNING:Xst:647 - Input <bEnableClear> is never used.
WARNING:Xst:647 - Input <mIoRegisterWt_n> is never used.
WARNING:Xst:647 - Input <mIoRd_n> is never used.
WARNING:Xst:647 - Input <mIoDataIn> is never used.
WARNING:Xst:647 - Input <MiteClk> is never used.
WARNING:Xst:647 - Input <aReset<0>> is never used.
WARNING:Xst:647 - Input <bEnableIn> is never used.
WARNING:Xst:647 - Input <mIoWt_n> is never used.
WARNING:Xst:647 - Input <mIoAddr> is never used.
WARNING:Xst:647 - Input <bTimeout> is never used.
WARNING:Xst:647 - Input <mIoRegisterDataIn> is never used.
WARNING:Xst:647 - Input <mIoDevSel_n> is never used.
WARNING:Xst:647 - Input <mDmaAck_n> is never used.
WARNING:Xst:647 - Input <bDataIn> is never used.
WARNING:Xst:1780 - Signal <bResetForFifo> is never used or assigned.
WARNING:Xst:1780 - Signal <mResetDone> is never used or assigned.
WARNING:Xst:1780 - Signal <mResetForFifo> is never used or assigned.
WARNING:Xst:1780 - Signal <bDisable> is never used or assigned.
WARNING:Xst:1780 - Signal <bDataOutFromFifo> is never used or assigned.
WARNING:Xst:1780 - Signal <bEnableOutLoc> is never used or assigned.
WARNING:Xst:1780 - Signal <bPushPop> is never used or assigned.
WARNING:Xst:1780 - Signal <bFlagFromFifo> is never used or assigned.
WARNING:Xst:1780 - Signal <mResetBitFromRegister> is never used or assigned.
Unit <MiteDmaComponent_3> synthesized.


Synthesizing Unit <RegisterAccess32>.
    Related source file is "C:/NIFPGA85/srvrTmp/LOCALH~1/TEST_F~1/RegisterAccess32.vhd".
WARNING:Xst:647 - Input <mIoAddr<1:0>> is never used.
WARNING:Xst:646 - Signal <mTmpFmWkWrite<0>> is assigned but never used.
WARNING:Xst:1780 - Signal <mIntIoReady> is never used or assigned.
    Found finite state machine <FSM_2> for signal <mWriteState>.
    -----------------------------------------------------------------------
    | States             | 3                                              |
    | Transitions        | 7                                              |
    | Inputs             | 3                                              |
    | Outputs            | 3                                              |
    | Clock              | MiteClk (rising_edge)                          |
    | Reset              | aMiteReset<0> (positive)                       |
    | Reset type         | asynchronous                                   |
    | Reset State        | idle                                           |
    | Power Up State     | idle                                           |
    | Encoding           | automatic                                      |
    | Implementation     | automatic                                      |
    -----------------------------------------------------------------------
    Found finite state machine <FSM_3> for signal <mReadState>.
    -----------------------------------------------------------------------
    | States             | 3                                              |
    | Transitions        | 7                                              |
    | Inputs             | 3                                              |
    | Outputs            | 3                                              |
    | Clock              | MiteClk (rising_edge)                          |
    | Reset              | aMiteReset<0> (positive)                       |
    | Reset type         | asynchronous                                   |
    | Reset State        | idle                                           |
    | Power Up State     | idle                                           |
    | Encoding           | automatic                                      |
    | Implementation     | automatic                                      |
    -----------------------------------------------------------------------
    Found 32-bit register for signal <mRegPortIn.Data>.
    Found 13-bit register for signal <mRegPortIn.Address>.
    Found 1-bit register for signal <mRegPortIn.Rd<0>>.
    Found 1-bit register for signal <mRegPortIn.Wt<0>>.
    Found 16-bit up counter for signal <mCount>.
    Found 32-bit register for signal <mQ>.
    Found 1-bit register for signal <mReadIoReady<0>>.
    Found 1-bit register for signal <mWriteIoReady<0>>.
    Summary:
	inferred   2 Finite State Machine(s).
	inferred   1 Counter(s).
	inferred  81 D-type flip-flop(s).
Unit <RegisterAccess32> synthesized.


Synthesizing Unit <HandshakeBase_3>.
    Related source file is "C:/NIFPGA85/srvrTmp/LOCALH~1/TEST_F~1/HandshakeBase.vhd".
WARNING:Xst:646 - Signal <oDlyDataAck<0>> is assigned but never used.
    Found 1-bit register for signal <oDataValid<0>>.
    Found 5-bit register for signal <oData>.
    Found 1-bit register for signal <iDlyPush<0>>.
    Found 1-bit register for signal <iLclReady<0>>.
    Found 1-bit xor2 for signal <iLclReady_0$xor0000> created at line 226.
    Found 5-bit register for signal <iLclStoredData>.
    Found 1-bit register for signal <iPushToggle<0>>.
    Found 1-bit register for signal <iRdyPushToggle<0>>.
    Found 1-bit register for signal <iRdyPushToggle_ms<0>>.
    Found 1-bit register for signal <iReset<0>>.
    Found 1-bit register for signal <iReset_ms<0>>.
    Found 1-bit register for signal <oDataAckRisingEdge<0>>.
    Found 1-bit register for signal <oDlyPushToggleChanged<0>>.
    Found 1-bit register for signal <oPushToggle0_ms<0>>.
    Found 1-bit register for signal <oPushToggle1<0>>.
    Found 1-bit register for signal <oPushToggle2<0>>.
    Found 1-bit xor2 for signal <oPushToggleChanged<0>>.
    Found 1-bit register for signal <oPushToggleChangeStored<0>>.
    Found 1-bit register for signal <oPushToggleToReady<0>>.
    Summary:
	inferred  25 D-type flip-flop(s).
Unit <HandshakeBase_3> synthesized.


Synthesizing Unit <TerminalRegister>.
    Related source file is "C:/NIFPGA85/srvrTmp/LOCALH~1/TEST_F~1/TerminalRegister.vhd".
    Found 1-bit register for signal <cQ<0>>.
    Summary:
	inferred   1 D-type flip-flop(s).
Unit <TerminalRegister> synthesized.


Synthesizing Unit <XNode_h2c45410_n99e98cc_0aad9e10>.
    Related source file is "C:/NIFPGA85/srvrTmp/LOCALH~1/TEST_F~1/XNode_h2c45410_n99e98cc_0aad9e10.vhd".
WARNING:Xst:646 - Signal <s0ac2ae70> is assigned but never used.
Unit <XNode_h2c45410_n99e98cc_0aad9e10> synthesized.


Synthesizing Unit <timedLoop_0060>.
    Related source file is "C:/NIFPGA85/srvrTmp/LOCALH~1/TEST_F~1/timedLoop_0060.vhd".
WARNING:Xst:647 - Input <iClkSubdiag_done> is never used.
WARNING:Xst:1780 - Signal <iSubdiagDone> is never used or assigned.
Unit <timedLoop_0060> synthesized.


Synthesizing Unit <testaviaFPGACompileCopy1result0>.
    Related source file is "C:/NIFPGA85/srvrTmp/LOCALH~1/TEST_F~1/testaviaFPGACompileCopy1result0.vhd".
WARNING:Xst:647 - Input <registerClockHostReadFromReshold<1>> is never used.
WARNING:Xst:647 - Input <registerClockHostWriteFromReshold<1>> is never used.
WARNING:Xst:1780 - Signal <rFpgaQualifiedReadEnableIn> is never used or assigned.
WARNING:Xst:1780 - Signal <rFpgaDataOut> is never used or assigned.
WARNING:Xst:1780 - Signal <rFpgaRead> is never used or assigned.
WARNING:Xst:1780 - Signal <rFpgaDataEnable> is never used or assigned.
WARNING:Xst:1780 - Signal <rFpgaDelayedReadEnableIn> is never used or assigned.
    Found 1-bit register for signal <registerClockFpgaWriteToReshold<0>>.
    Found 1-bit register for signal <rFpgaDelayedWriteEnableIn<0>>.
    Summary:
	inferred   2 D-type flip-flop(s).
Unit <testaviaFPGACompileCopy1result0> synthesized.


Synthesizing Unit <arb_rw_0AFB6A90_0073>.
    Related source file is "C:/NIFPGA85/srvrTmp/LOCALH~1/TEST_F~1/arb_rw_0AFB6A90_0073.vhd".
Unit <arb_rw_0AFB6A90_0073> synthesized.


Synthesizing Unit <arb_rw_0AE9A608_0074>.
    Related source file is "C:/NIFPGA85/srvrTmp/LOCALH~1/TEST_F~1/arb_rw_0AE9A608_0074.vhd".
Unit <arb_rw_0AE9A608_0074> synthesized.


Synthesizing Unit <arb_rw_0B0C5CC8_0075>.
    Related source file is "C:/NIFPGA85/srvrTmp/LOCALH~1/TEST_F~1/arb_rw_0B0C5CC8_0075.vhd".
Unit <arb_rw_0B0C5CC8_0075> synthesized.


Synthesizing Unit <arb_rw_0B0CE1D0_0076>.
    Related source file is "C:/NIFPGA85/srvrTmp/LOCALH~1/TEST_F~1/arb_rw_0B0CE1D0_0076.vhd".
Unit <arb_rw_0B0CE1D0_0076> synthesized.


Synthesizing Unit <arb_rw_0B0C1B48_0077>.
    Related source file is "C:/NIFPGA85/srvrTmp/LOCALH~1/TEST_F~1/arb_rw_0B0C1B48_0077.vhd".
Unit <arb_rw_0B0C1B48_0077> synthesized.


Synthesizing Unit <arb_rw_0B0C3710_0078>.
    Related source file is "C:/NIFPGA85/srvrTmp/LOCALH~1/TEST_F~1/arb_rw_0B0C3710_0078.vhd".
Unit <arb_rw_0B0C3710_0078> synthesized.


Synthesizing Unit <arb_rw_0B0CC8D8_0079>.
    Related source file is "C:/NIFPGA85/srvrTmp/LOCALH~1/TEST_F~1/arb_rw_0B0CC8D8_0079.vhd".
Unit <arb_rw_0B0CC8D8_0079> synthesized.


Synthesizing Unit <arb_rw_0B0CD520_007a>.
    Related source file is "C:/NIFPGA85/srvrTmp/LOCALH~1/TEST_F~1/arb_rw_0B0CD520_007a.vhd".
Unit <arb_rw_0B0CD520_007a> synthesized.


Synthesizing Unit <cpdarith_0031>.
    Related source file is "C:/NIFPGA85/srvrTmp/LOCALH~1/TEST_F~1/cpdarith_0031.vhd".
WARNING:Xst:646 - Signal <eiDelayed<0>> is assigned but never used.
Unit <cpdarith_0031> synthesized.


Synthesizing Unit <demux_Fascade_02C45410_0ACD5AF4>.
    Related source file is "C:/NIFPGA85/srvrTmp/LOCALH~1/TEST_F~1/demux_Fascade_02C45410_0acd5af4.vhd".
WARNING:Xst:646 - Signal <eo0000001e> is assigned but never used.
Unit <demux_Fascade_02C45410_0ACD5AF4> synthesized.


Synthesizing Unit <demux_Fascade_02C45410_0ABE80B4>.
    Related source file is "C:/NIFPGA85/srvrTmp/LOCALH~1/TEST_F~1/demux_Fascade_02C45410_0abe80b4.vhd".
WARNING:Xst:646 - Signal <eo0000003b> is assigned but never used.
Unit <demux_Fascade_02C45410_0ABE80B4> synthesized.


Synthesizing Unit <NiLvFxpCoerce>.
    Related source file is "C:/NIFPGA85/srvrTmp/LOCALH~1/TEST_F~1/NiLvFxpCoerce.vhd".
Unit <NiLvFxpCoerce> synthesized.


Synthesizing Unit <HandshakeSLV_1>.
    Related source file is "C:/NIFPGA85/srvrTmp/LOCALH~1/TEST_F~1/HandshakeSLV.vhd".
Unit <HandshakeSLV_1> synthesized.


Synthesizing Unit <HandshakeSLV_2>.
    Related source file is "C:/NIFPGA85/srvrTmp/LOCALH~1/TEST_F~1/HandshakeSLV.vhd".
Unit <HandshakeSLV_2> synthesized.


Synthesizing Unit <RegisterAccess>.
    Related source file is "C:/NIFPGA85/srvrTmp/LOCALH~1/TEST_F~1/RegisterAccess.vhd".
WARNING:Xst:647 - Input <mDmaAccess> is never used.
WARNING:Xst:647 - Input <aReset<0>> is never used.
Unit <RegisterAccess> synthesized.


Synthesizing Unit <HandshakeSLV_3>.
    Related source file is "C:/NIFPGA85/srvrTmp/LOCALH~1/TEST_F~1/HandshakeSLV.vhd".
Unit <HandshakeSLV_3> synthesized.


Synthesizing Unit <XNode_h2c45410_n99e944c_0ab3a308>.
    Related source file is "C:/NIFPGA85/srvrTmp/LOCALH~1/TEST_F~1/XNode_h2c45410_n99e944c_0ab3a308.vhd".
Unit <XNode_h2c45410_n99e944c_0ab3a308> synthesized.


Synthesizing Unit <prim_CVT_Fascade_02C45410_0AB39BD0>.
    Related source file is "C:/NIFPGA85/srvrTmp/LOCALH~1/TEST_F~1/prim_CVT_Fascade_02C45410_0ab39bd0.vhd".
Unit <prim_CVT_Fascade_02C45410_0AB39BD0> synthesized.


Synthesizing Unit <prim_CVT_Fascade_02C45410_09A2DC60>.
    Related source file is "C:/NIFPGA85/srvrTmp/LOCALH~1/TEST_F~1/prim_CVT_Fascade_02C45410_09a2dc60.vhd".
Unit <prim_CVT_Fascade_02C45410_09A2DC60> synthesized.


Synthesizing Unit <bushold>.
    Related source file is "C:/NIFPGA85/srvrTmp/LOCALH~1/TEST_F~1/bushold.vhd".
WARNING:Xst:647 - Input <miteClkFromResViControlHostWrite<0>> is never used.
WARNING:Xst:1305 - Output <dummyToReshold> is never assigned. Tied to value 0.
WARNING:Xst:1305 - Output <miteClkToResViSignatureHostRead<1>> is never assigned. Tied to value 0.
WARNING:Xst:1305 - Output <clk40ToRestestaviaFPGACompileCopy1result0HostRead<1>> is never assigned. Tied to value 0.
WARNING:Xst:647 - Input <dummyFromReshold> is never used.
WARNING:Xst:1305 - Output <miteClkToResViControlHostRead<1>> is never assigned. Tied to value 0.
WARNING:Xst:1305 - Output <clk40ToRestestaviaFPGACompileCopy1result0HostWrite<1>> is never assigned. Tied to value 0.
WARNING:Xst:1305 - Output <miteClkToResViControlHostWrite<1>> is never assigned. Tied to value 0.
WARNING:Xst:647 - Input <clk40FromRestestaviaFPGACompileCopy1result0HostWrite<0>> is never used.
WARNING:Xst:1780 - Signal <Clk40WideDataValid> is never used or assigned.
WARNING:Xst:646 - Signal <Clk40Ready<0>> is assigned but never used.
WARNING:Xst:646 - Signal <MiteClkReady<0>> is assigned but never used.
WARNING:Xst:1780 - Signal <Clk40HSDataOut> is never used or assigned.
WARNING:Xst:1780 - Signal <Clk40ReadToWide> is never used or assigned.
WARNING:Xst:1780 - Signal <Clk40Push> is never used or assigned.
WARNING:Xst:646 - Signal <MiteClkWideWrite> is assigned but never used.
WARNING:Xst:1780 - Signal <Clk40SrDataOut> is never used or assigned.
WARNING:Xst:646 - Signal <Clk40RegDataIn<31:1>> is assigned but never used.
WARNING:Xst:646 - Signal <Clk40WideDataOut> is assigned but never used.
WARNING:Xst:653 - Signal <cRegWrite<0>> is used but never assigned. Tied to value 0.
WARNING:Xst:646 - Signal <Clk40WideWrite> is assigned but never used.
WARNING:Xst:1780 - Signal <MiteClkPush> is never used or assigned.
WARNING:Xst:1780 - Signal <Clk40WideDataIn> is never used or assigned.
WARNING:Xst:646 - Signal <MiteClkWideDataIn> is assigned but never used.
WARNING:Xst:1780 - Signal <Clk40WideAccess> is never used or assigned.
WARNING:Xst:646 - Signal <Clk40WideRead> is assigned but never used.
WARNING:Xst:1780 - Signal <Clk40SrCount<30:1>> is never used or assigned.
WARNING:Xst:653 - Signal <Clk40SrCount<0>> is used but never assigned. Tied to value 0.
WARNING:Xst:646 - Signal <MiteClkSrCount<30:4>> is assigned but never used.
WARNING:Xst:653 - Signal <cRegRead<0>> is used but never assigned. Tied to value 0.
WARNING:Xst:1780 - Signal <Clk40WriteToWide> is never used or assigned.
WARNING:Xst:1780 - Signal <MiteClkHSDataOut> is never used or assigned.
WARNING:Xst:646 - Signal <cCount<0>> is assigned but never used.
    Found 13-bit comparator greatequal for signal <iPush_0$cmp_ge0000> created at line 162.
    Found 13-bit comparator less for signal <iPush_0$cmp_lt0000> created at line 162.
    Summary:
	inferred   2 Comparator(s).
Unit <bushold> synthesized.


Synthesizing Unit <XNode_h2c45410_n99e28cc_0acd9720>.
    Related source file is "C:/NIFPGA85/srvrTmp/LOCALH~1/TEST_F~1/XNode_h2c45410_n99e28cc_0acd9720.vhd".
Unit <XNode_h2c45410_n99e28cc_0acd9720> synthesized.


Synthesizing Unit <MiteIrq>.
    Related source file is "C:/NIFPGA85/srvrTmp/LOCALH~1/TEST_F~1/MiteIrq.vhd".
WARNING:Xst:647 - Input <IrqStatusClk> is never used.
WARNING:Xst:647 - Input <iIrqStatusEnableClear> is never used.
    Found 1-bit register for signal <iIrqEnableOut>.
    Found 1-bit register for signal <iIrqEnableInDly>.
    Found 1-bit register for signal <iPushIrqNumState<0>>.
    Found 1-bit register for signal <mIEReg>.
    Found 1-bit register for signal <mIoReadDly<0>>.
    Found 1-bit register for signal <mIoWriteDly<0>>.
    Found 32-bit register for signal <mMaskReg>.
    Found 1-bit register for signal <mStartOfRead<0>>.
    Found 1-bit register for signal <mStartOfWrite<0>>.
    Found 32-bit register for signal <mStatusReg>.
    Summary:
	inferred  72 D-type flip-flop(s).
Unit <MiteIrq> synthesized.


Synthesizing Unit <rvi_test_vi_FPGACompileCopy1_0A278380>.
    Related source file is "C:/NIFPGA85/srvrTmp/LOCALH~1/TEST_F~1/rvi_test_vi_FPGACompileCopy1_0a278380.vhd".
WARNING:Xst:647 - Input <iteration> is never used.
Unit <rvi_test_vi_FPGACompileCopy1_0A278380> synthesized.


Synthesizing Unit <MiteInterface>.
    Related source file is "C:/NIFPGA85/srvrTmp/LOCALH~1/TEST_F~1/MiteInterface.vhd".
WARNING:Xst:647 - Input <IrqStatusClkArray<0>> is never used.
WARNING:Xst:1780 - Signal <mDmaEnableArray> is never used or assigned.
WARNING:Xst:1780 - Signal <mIoIrqManagerDataOut> is never used or assigned.
WARNING:Xst:1780 - Signal <bIrqIntStatus> is never used or assigned.
    Found 1-bit tristate buffer for signal <mIoDtack_n>.
    Found 1-bit register for signal <mDtack<0>>.
    Found 1-bit register for signal <mDtackOE<0>>.
    Summary:
	inferred   2 D-type flip-flop(s).
	inferred   1 Tristate(s).
Unit <MiteInterface> synthesized.


Synthesizing Unit <Interface>.
    Related source file is "C:/NIFPGA85/srvrTmp/LOCALH~1/TEST_F~1/Interface.vhd".
WARNING:Xst:1305 - Output <mDmaReady> is never assigned. Tied to value 0.
WARNING:Xst:1305 - Output <mIrq> is never assigned. Tied to value 0.
WARNING:Xst:653 - Signal <IrqStatusClkArray<0>> is used but never assigned. Tied to value 0.
WARNING:Xst:646 - Signal <mIrqVec<0>> is assigned but never used.
WARNING:Xst:646 - Signal <DmaFlagArray> is assigned but never used.
WARNING:Xst:653 - Signal <bIrqStatusOutArray<0>.EnableClear> is used but never assigned. Tied to value 0.
WARNING:Xst:653 - Signal <bIrqOutArray<0>.IrqNum> is used but never assigned. Tied to value 00000.
WARNING:Xst:646 - Signal <bIrqStatusInArray<0>.Status> is assigned but never used.
WARNING:Xst:1781 - Signal <DmaTimeoutArray> is used but never assigned. Tied to default value.
WARNING:Xst:653 - Signal <DmaEnableClearArray> is used but never assigned. Tied to value 000.
WARNING:Xst:646 - Signal <DmaEnableOutArray> is assigned but never used.
WARNING:Xst:1781 - Signal <DmaDataInArray> is used but never assigned. Tied to default value.
WARNING:Xst:646 - Signal <bIrqStatusInArray<0>.EnableOut> is assigned but never used.
WARNING:Xst:646 - Signal <bIrqInArray<0>.EnableOut> is assigned but never used.
WARNING:Xst:653 - Signal <DmaEnableInArray> is used but never assigned. Tied to value 000.
WARNING:Xst:653 - Signal <IrqClkArray<0>> is used but never assigned. Tied to value 0.
WARNING:Xst:653 - Signal <bIrqOutArray<0>.EnableClear> is used but never assigned. Tied to value 0.
WARNING:Xst:653 - Signal <DmaClkArray> is used but never assigned. Tied to value 000.
WARNING:Xst:646 - Signal <DmaDataOutArray> is assigned but never used.
WARNING:Xst:653 - Signal <bIrqStatusOutArray<0>.EnableIn> is used but never assigned. Tied to value 0.
WARNING:Xst:653 - Signal <bIrqOutArray<0>.EnableIn> is used but never assigned. Tied to value 0.
Unit <Interface> synthesized.


Synthesizing Unit <rvi_test_vi_FPGACompileCopy1>.
    Related source file is "C:/NIFPGA85/srvrTmp/LOCALH~1/TEST_F~1/rvi_test_vi_FPGACompileCopy1.vhd".
WARNING:Xst:646 - Signal <li00000032> is assigned but never used.
WARNING:Xst:1780 - Signal <lTimingOut00000032> is never used or assigned.
Unit <rvi_test_vi_FPGACompileCopy1> synthesized.


Synthesizing Unit <toplevel_gen>.
    Related source file is "C:/NIFPGA85/srvrTmp/LOCALH~1/TEST_F~1/toplevel_gen.vhd".
WARNING:Xst:2565 - Inout <configd<0>> is never assigned.
WARNING:Xst:2565 - Inout <configd<1>> is never assigned.
WARNING:Xst:2565 - Inout <configd<2>> is never assigned.
WARNING:Xst:647 - Input <iohword_n> is never used.
WARNING:Xst:2565 - Inout <configd<3>> is never assigned.
WARNING:Xst:2565 - Inout <temp_miso> is never assigned.
WARNING:Xst:2565 - Inout <dio_00> is never assigned.
WARNING:Xst:2565 - Inout <dio_01> is never assigned.
WARNING:Xst:2565 - Inout <dio_02> is never assigned.
WARNING:Xst:2565 - Inout <dio_03> is never assigned.
WARNING:Xst:2565 - Inout <dio_04> is never assigned.
WARNING:Xst:2565 - Inout <dio_10> is never assigned.
WARNING:Xst:2565 - Inout <dio_05> is never assigned.
WARNING:Xst:2565 - Inout <dio_11> is never assigned.
WARNING:Xst:2565 - Inout <dio_06> is never assigned.
WARNING:Xst:2565 - Inout <dio_12> is never assigned.
WARNING:Xst:2565 - Inout <dio_07> is never assigned.
WARNING:Xst:2565 - Inout <dio_13> is never assigned.
WARNING:Xst:2565 - Inout <dio_08> is never assigned.
WARNING:Xst:2565 - Inout <dio_14> is never assigned.
WARNING:Xst:2565 - Inout <dio_09> is never assigned.
WARNING:Xst:2565 - Inout <dio_20> is never assigned.
WARNING:Xst:2565 - Inout <dio_15> is never assigned.
WARNING:Xst:2565 - Inout <dio_21> is never assigned.
WARNING:Xst:2565 - Inout <dio_16> is never assigned.
WARNING:Xst:2565 - Inout <dio_22> is never assigned.
WARNING:Xst:2565 - Inout <dio_17> is never assigned.
WARNING:Xst:2565 - Inout <dio_23> is never assigned.
WARNING:Xst:2565 - Inout <dio_18> is never assigned.
WARNING:Xst:2565 - Inout <dio_24> is never assigned.
WARNING:Xst:2565 - Inout <dio_19> is never assigned.
WARNING:Xst:2565 - Inout <dio_30> is never assigned.
WARNING:Xst:2565 - Inout <dio_25> is never assigned.
WARNING:Xst:2565 - Inout <dio_31> is never assigned.
WARNING:Xst:2565 - Inout <dio_26> is never assigned.
WARNING:Xst:2565 - Inout <dio_32> is never assigned.
WARNING:Xst:2565 - Inout <dio_27> is never assigned.
WARNING:Xst:2565 - Inout <dio_33> is never assigned.
WARNING:Xst:2565 - Inout <dio_28> is never assigned.
WARNING:Xst:2565 - Inout <dio_34> is never assigned.
WARNING:Xst:2565 - Inout <dio_29> is never assigned.
WARNING:Xst:2565 - Inout <dio_40> is never assigned.
WARNING:Xst:2565 - Inout <dio_35> is never assigned.
WARNING:Xst:2565 - Inout <dio_41> is never assigned.
WARNING:Xst:2565 - Inout <dio_36> is never assigned.
WARNING:Xst:2565 - Inout <dio_42> is never assigned.
WARNING:Xst:2565 - Inout <dio_37> is never assigned.
WARNING:Xst:2565 - Inout <dio_43> is never assigned.
WARNING:Xst:2565 - Inout <dio_38> is never assigned.
WARNING:Xst:2565 - Inout <dio_44> is never assigned.
WARNING:Xst:2565 - Inout <dio_39> is never assigned.
WARNING:Xst:2565 - Inout <dio_50> is never assigned.
WARNING:Xst:2565 - Inout <dio_45> is never assigned.
WARNING:Xst:2565 - Inout <dio_51> is never assigned.
WARNING:Xst:2565 - Inout <dio_46> is never assigned.
WARNING:Xst:2565 - Inout <dio_52> is never assigned.
WARNING:Xst:2565 - Inout <dio_47> is never assigned.
WARNING:Xst:2565 - Inout <dio_53> is never assigned.
WARNING:Xst:2565 - Inout <dio_48> is never assigned.
WARNING:Xst:2565 - Inout <dio_54> is never assigned.
WARNING:Xst:2565 - Inout <dio_49> is never assigned.
WARNING:Xst:2565 - Inout <dio_60> is never assigned.
WARNING:Xst:2565 - Inout <dio_55> is never assigned.
WARNING:Xst:2565 - Inout <dio_61> is never assigned.
WARNING:Xst:2565 - Inout <dio_56> is never assigned.
WARNING:Xst:2565 - Inout <dio_62> is never assigned.
WARNING:Xst:2565 - Inout <dio_57> is never assigned.
WARNING:Xst:2565 - Inout <dio_63> is never assigned.
WARNING:Xst:2565 - Inout <dio_58> is never assigned.
WARNING:Xst:2565 - Inout <dio_64> is never assigned.
WARNING:Xst:2565 - Inout <dio_59> is never assigned.
WARNING:Xst:2565 - Inout <dio_70> is never assigned.
WARNING:Xst:2565 - Inout <dio_65> is never assigned.
WARNING:Xst:2565 - Inout <dio_71> is never assigned.
WARNING:Xst:2565 - Inout <dio_66> is never assigned.
WARNING:Xst:2565 - Inout <dio_72> is never assigned.
WARNING:Xst:2565 - Inout <dio_67> is never assigned.
WARNING:Xst:2565 - Inout <dio_73> is never assigned.
WARNING:Xst:2565 - Inout <dio_68> is never assigned.
WARNING:Xst:2565 - Inout <dio_74> is never assigned.
WARNING:Xst:2565 - Inout <dio_69> is never assigned.
WARNING:Xst:2565 - Inout <dio_75> is never assigned.
WARNING:Xst:2565 - Inout <dio_76> is never assigned.
WARNING:Xst:2565 - Inout <dio_77> is never assigned.
WARNING:Xst:2565 - Inout <dio_78> is never assigned.
WARNING:Xst:2565 - Inout <dio_79> is never assigned.
WARNING:Xst:1780 - Signal <ctrl_reset> is never used or assigned.
WARNING:Xst:1780 - Signal <mViControl> is never used or assigned.
WARNING:Xst:1780 - Signal <dio_enable_00> is never used or assigned.
WARNING:Xst:1780 - Signal <dio_enable_01> is never used or assigned.
WARNING:Xst:1780 - Signal <dio_enable_02> is never used or assigned.
WARNING:Xst:1780 - Signal <dio_enable_03> is never used or assigned.
WARNING:Xst:1780 - Signal <dio_enable_04> is never used or assigned.
WARNING:Xst:1780 - Signal <dio_enable_05> is never used or assigned.
WARNING:Xst:1780 - Signal <dio_enable_10> is never used or assigned.
WARNING:Xst:1780 - Signal <dio_enable_06> is never used or assigned.
WARNING:Xst:1780 - Signal <dio_enable_11> is never used or assigned.
WARNING:Xst:1780 - Signal <dio_enable_07> is never used or assigned.
WARNING:Xst:1780 - Signal <dio_enable_12> is never used or assigned.
WARNING:Xst:1780 - Signal <dio_enable_08> is never used or assigned.
WARNING:Xst:1780 - Signal <dio_enable_13> is never used or assigned.
WARNING:Xst:1780 - Signal <dio_enable_09> is never used or assigned.
WARNING:Xst:1780 - Signal <dio_enable_14> is never used or assigned.
WARNING:Xst:1780 - Signal <dio_enable_15> is never used or assigned.
WARNING:Xst:1780 - Signal <dio_enable_20> is never used or assigned.
WARNING:Xst:1780 - Signal <dio_enable_16> is never used or assigned.
WARNING:Xst:1780 - Signal <dio_enable_21> is never used or assigned.
WARNING:Xst:1780 - Signal <dio_enable_17> is never used or assigned.
WARNING:Xst:1780 - Signal <dio_enable_22> is never used or assigned.
WARNING:Xst:1780 - Signal <FPGA_temperature_miso> is never used or assigned.
WARNING:Xst:1780 - Signal <dio_enable_18> is never used or assigned.
WARNING:Xst:1780 - Signal <dio_enable_23> is never used or assigned.
WARNING:Xst:1780 - Signal <dio_enable_19> is never used or assigned.
WARNING:Xst:1780 - Signal <dio_enable_24> is never used or assigned.
WARNING:Xst:1780 - Signal <dio_enable_25> is never used or assigned.
WARNING:Xst:1780 - Signal <dio_enable_30> is never used or assigned.
WARNING:Xst:1780 - Signal <ctrl_data> is never used or assigned.
WARNING:Xst:1780 - Signal <dio_enable_26> is never used or assigned.
WARNING:Xst:1780 - Signal <dio_enable_31> is never used or assigned.
WARNING:Xst:1780 - Signal <dio_enable_27> is never used or assigned.
WARNING:Xst:1780 - Signal <dio_enable_32> is never used or assigned.
WARNING:Xst:1780 - Signal <dio_enable_28> is never used or assigned.
WARNING:Xst:1780 - Signal <dio_enable_33> is never used or assigned.
WARNING:Xst:1780 - Signal <dio_enable_29> is never used or assigned.
WARNING:Xst:1780 - Signal <dio_enable_34> is never used or assigned.
WARNING:Xst:1780 - Signal <dio_enable_35> is never used or assigned.
WARNING:Xst:1780 - Signal <dio_enable_40> is never used or assigned.
WARNING:Xst:1780 - Signal <dio_enable_36> is never used or assigned.
WARNING:Xst:1780 - Signal <dio_enable_41> is never used or assigned.
WARNING:Xst:1780 - Signal <dio_enable_37> is never used or assigned.
WARNING:Xst:1780 - Signal <dio_enable_42> is never used or assigned.
WARNING:Xst:1780 - Signal <dio_enable_38> is never used or assigned.
WARNING:Xst:1780 - Signal <dio_enable_43> is never used or assigned.
WARNING:Xst:1780 - Signal <dio_enable_39> is never used or assigned.
WARNING:Xst:1780 - Signal <dio_enable_44> is never used or assigned.
WARNING:Xst:1780 - Signal <dio_enable_50> is never used or assigned.
WARNING:Xst:1780 - Signal <dio_enable_45> is never used or assigned.
WARNING:Xst:1780 - Signal <dio_enable_51> is never used or assigned.
WARNING:Xst:1780 - Signal <dio_enable_46> is never used or assigned.
WARNING:Xst:1780 - Signal <dio_enable_52> is never used or assigned.
WARNING:Xst:1780 - Signal <dio_enable_47> is never used or assigned.
WARNING:Xst:1780 - Signal <dio_enable_53> is never used or assigned.
WARNING:Xst:1780 - Signal <dio_enable_48> is never used or assigned.
WARNING:Xst:1780 - Signal <dio_enable_54> is never used or assigned.
WARNING:Xst:1780 - Signal <dio_enable_49> is never used or assigned.
WARNING:Xst:1780 - Signal <dio_enable_60> is never used or assigned.
WARNING:Xst:1780 - Signal <dio_enable_55> is never used or assigned.
WARNING:Xst:1780 - Signal <dio_enable_61> is never used or assigned.
WARNING:Xst:1780 - Signal <dio_enable_56> is never used or assigned.
WARNING:Xst:1780 - Signal <dio_enable_62> is never used or assigned.
WARNING:Xst:1780 - Signal <dio_enable_57> is never used or assigned.
WARNING:Xst:1780 - Signal <dio_enable_63> is never used or assigned.
WARNING:Xst:1780 - Signal <dio_enable_58> is never used or assigned.
WARNING:Xst:1780 - Signal <dio_enable_64> is never used or assigned.
WARNING:Xst:1780 - Signal <dio_enable_59> is never used or assigned.
WARNING:Xst:1780 - Signal <dio_enable_70> is never used or assigned.
WARNING:Xst:1780 - Signal <dio_enable_65> is never used or assigned.
WARNING:Xst:1780 - Signal <dio_enable_71> is never used or assigned.
WARNING:Xst:1780 - Signal <dio_enable_66> is never used or assigned.
WARNING:Xst:1780 - Signal <dio_enable_72> is never used or assigned.
WARNING:Xst:1780 - Signal <dio_enable_67> is never used or assigned.
WARNING:Xst:1780 - Signal <dio_enable_73> is never used or assigned.
WARNING:Xst:1780 - Signal <dio_enable_68> is never used or assigned.
WARNING:Xst:1780 - Signal <dio_enable_74> is never used or assigned.
WARNING:Xst:1780 - Signal <dio_enable_69> is never used or assigned.
WARNING:Xst:1780 - Signal <dio_enable_75> is never used or assigned.
WARNING:Xst:1780 - Signal <dio_enable_76> is never used or assigned.
WARNING:Xst:1780 - Signal <dio_enable_77> is never used or assigned.
WARNING:Xst:1780 - Signal <dio_enable_78> is never used or assigned.
WARNING:Xst:1780 - Signal <dio_enable_79> is never used or assigned.
WARNING:Xst:1780 - Signal <ctrl_decode> is never used or assigned.
WARNING:Xst:1780 - Signal <irqStatus> is never used or assigned.
WARNING:Xst:1780 - Signal <gCtl_decode> is never used or assigned.
WARNING:Xst:1780 - Signal <control_reset> is never used or assigned.
WARNING:Xst:1780 - Signal <gCtl_out> is never used or assigned.
WARNING:Xst:1780 - Signal <enable_out_sig> is never used or assigned.
WARNING:Xst:1780 - Signal <mitereset> is never used or assigned.
WARNING:Xst:1780 - Signal <ctrl_e_in> is never used or assigned.
WARNING:Xst:1780 - Signal <iorReg1> is never used or assigned.
WARNING:Xst:1780 - Signal <iorReg2> is never used or assigned.
WARNING:Xst:1780 - Signal <ctrl_in> is never used or assigned.
WARNING:Xst:1780 - Signal <iowReg1> is never used or assigned.
WARNING:Xst:1780 - Signal <iowReg2> is never used or assigned.
WARNING:Xst:1780 - Signal <irqFromAp> is never used or assigned.
WARNING:Xst:1780 - Signal <ctrl_e_out> is never used or assigned.
WARNING:Xst:1780 - Signal <ior_qualified> is never used or assigned.
WARNING:Xst:1780 - Signal <mRegisterAccess> is never used or assigned.
WARNING:Xst:1780 - Signal <dio_output_indiv_00> is never used or assigned.
WARNING:Xst:1780 - Signal <dio_output_indiv_01> is never used or assigned.
WARNING:Xst:1780 - Signal <dio_output_indiv_02> is never used or assigned.
WARNING:Xst:1780 - Signal <dio_output_indiv_03> is never used or assigned.
WARNING:Xst:1780 - Signal <dio_output_indiv_04> is never used or assigned.
WARNING:Xst:1780 - Signal <dio_output_indiv_05> is never used or assigned.
WARNING:Xst:1780 - Signal <dio_output_indiv_10> is never used or assigned.
WARNING:Xst:1780 - Signal <dio_output_indiv_06> is never used or assigned.
WARNING:Xst:1780 - Signal <dio_output_indiv_11> is never used or assigned.
WARNING:Xst:1780 - Signal <dio_output_indiv_07> is never used or assigned.
WARNING:Xst:1780 - Signal <dio_output_indiv_12> is never used or assigned.
WARNING:Xst:1780 - Signal <dio_output_indiv_08> is never used or assigned.
WARNING:Xst:1780 - Signal <dio_output_indiv_13> is never used or assigned.
WARNING:Xst:1780 - Signal <dio_output_indiv_09> is never used or assigned.
WARNING:Xst:1780 - Signal <dio_output_indiv_14> is never used or assigned.
WARNING:Xst:1780 - Signal <dio_output_indiv_15> is never used or assigned.
WARNING:Xst:1780 - Signal <dio_output_indiv_20> is never used or assigned.
WARNING:Xst:1780 - Signal <dio_output_indiv_16> is never used or assigned.
WARNING:Xst:1780 - Signal <dio_output_indiv_21> is never used or assigned.
WARNING:Xst:1780 - Signal <dio_output_indiv_17> is never used or assigned.
WARNING:Xst:1780 - Signal <dio_output_indiv_22> is never used or assigned.
WARNING:Xst:1780 - Signal <dio_output_indiv_18> is never used or assigned.
WARNING:Xst:1780 - Signal <dio_output_indiv_23> is never used or assigned.
WARNING:Xst:1780 - Signal <dio_output_indiv_19> is never used or assigned.
WARNING:Xst:1780 - Signal <dio_output_indiv_24> is never used or assigned.
WARNING:Xst:1780 - Signal <dio_output_indiv_25> is never used or assigned.
WARNING:Xst:1780 - Signal <dio_output_indiv_30> is never used or assigned.
WARNING:Xst:1780 - Signal <dio_output_indiv_26> is never used or assigned.
WARNING:Xst:1780 - Signal <dio_output_indiv_31> is never used or assigned.
WARNING:Xst:1780 - Signal <dio_output_indiv_27> is never used or assigned.
WARNING:Xst:1780 - Signal <dio_output_indiv_32> is never used or assigned.
WARNING:Xst:1780 - Signal <dio_output_indiv_28> is never used or assigned.
WARNING:Xst:1780 - Signal <dio_output_indiv_33> is never used or assigned.
WARNING:Xst:1780 - Signal <dio_output_indiv_29> is never used or assigned.
WARNING:Xst:1780 - Signal <dio_output_indiv_34> is never used or assigned.
WARNING:Xst:1780 - Signal <dio_output_indiv_35> is never used or assigned.
WARNING:Xst:1780 - Signal <dio_output_indiv_40> is never used or assigned.
WARNING:Xst:1780 - Signal <dio_output_indiv_36> is never used or assigned.
WARNING:Xst:1780 - Signal <dio_output_indiv_41> is never used or assigned.
WARNING:Xst:1780 - Signal <dio_output_indiv_37> is never used or assigned.
WARNING:Xst:1780 - Signal <dio_output_indiv_42> is never used or assigned.
WARNING:Xst:1780 - Signal <dio_output_indiv_38> is never used or assigned.
WARNING:Xst:1780 - Signal <dio_output_indiv_43> is never used or assigned.
WARNING:Xst:1780 - Signal <dio_output_indiv_39> is never used or assigned.
WARNING:Xst:1780 - Signal <dio_output_indiv_44> is never used or assigned.
WARNING:Xst:1780 - Signal <dio_output_indiv_50> is never used or assigned.
WARNING:Xst:1780 - Signal <dio_output_indiv_45> is never used or assigned.
WARNING:Xst:1780 - Signal <dio_output_indiv_51> is never used or assigned.
WARNING:Xst:1780 - Signal <dio_output_indiv_46> is never used or assigned.
WARNING:Xst:1780 - Signal <dio_output_indiv_52> is never used or assigned.
WARNING:Xst:1780 - Signal <dio_output_indiv_47> is never used or assigned.
WARNING:Xst:1780 - Signal <dio_output_indiv_53> is never used or assigned.
WARNING:Xst:1780 - Signal <dio_output_indiv_48> is never used or assigned.
WARNING:Xst:1780 - Signal <dio_output_indiv_54> is never used or assigned.
WARNING:Xst:1780 - Signal <dio_output_indiv_49> is never used or assigned.
WARNING:Xst:1780 - Signal <dio_output_indiv_60> is never used or assigned.
WARNING:Xst:1780 - Signal <dio_output_indiv_55> is never used or assigned.
WARNING:Xst:1780 - Signal <dio_output_indiv_61> is never used or assigned.
WARNING:Xst:1780 - Signal <dio_output_indiv_56> is never used or assigned.
WARNING:Xst:1780 - Signal <dio_output_indiv_62> is never used or assigned.
WARNING:Xst:1780 - Signal <dio_output_indiv_57> is never used or assigned.
WARNING:Xst:1780 - Signal <dio_output_indiv_63> is never used or assigned.
WARNING:Xst:1780 - Signal <dio_output_indiv_58> is never used or assigned.
WARNING:Xst:1780 - Signal <dio_output_indiv_64> is never used or assigned.
WARNING:Xst:1780 - Signal <dio_output_indiv_59> is never used or assigned.
WARNING:Xst:1780 - Signal <dio_output_indiv_70> is never used or assigned.
WARNING:Xst:1780 - Signal <dio_output_indiv_65> is never used or assigned.
WARNING:Xst:1780 - Signal <iow_qualified> is never used or assigned.
WARNING:Xst:1780 - Signal <dio_output_indiv_71> is never used or assigned.
WARNING:Xst:1780 - Signal <dio_output_indiv_66> is never used or assigned.
WARNING:Xst:1780 - Signal <dio_output_indiv_72> is never used or assigned.
WARNING:Xst:1780 - Signal <dio_output_indiv_67> is never used or assigned.
WARNING:Xst:1780 - Signal <dio_output_indiv_73> is never used or assigned.
WARNING:Xst:1780 - Signal <dio_output_indiv_68> is never used or assigned.
WARNING:Xst:1780 - Signal <dio_output_indiv_74> is never used or assigned.
WARNING:Xst:1780 - Signal <dio_output_indiv_69> is never used or assigned.
WARNING:Xst:1780 - Signal <dio_output_indiv_75> is never used or assigned.
WARNING:Xst:1780 - Signal <dio_output_indiv_76> is never used or assigned.
WARNING:Xst:1780 - Signal <dio_output_indiv_77> is never used or assigned.
WARNING:Xst:1780 - Signal <temperature_miso> is never used or assigned.
WARNING:Xst:1780 - Signal <dio_output_indiv_78> is never used or assigned.
WARNING:Xst:1780 - Signal <dio_output_indiv_79> is never used or assigned.
WARNING:Xst:646 - Signal <mDmaReady> is assigned but never used.
WARNING:Xst:1780 - Signal <dio_output_00> is never used or assigned.
WARNING:Xst:1780 - Signal <dio_output_01> is never used or assigned.
WARNING:Xst:1780 - Signal <dio_output_02> is never used or assigned.
WARNING:Xst:1780 - Signal <dio_output_03> is never used or assigned.
WARNING:Xst:1780 - Signal <dio_output_04> is never used or assigned.
WARNING:Xst:1780 - Signal <dio_enable_indiv_00> is never used or assigned.
WARNING:Xst:1780 - Signal <dio_output_05> is never used or assigned.
WARNING:Xst:1780 - Signal <dio_output_10> is never used or assigned.
WARNING:Xst:1780 - Signal <dio_enable_indiv_01> is never used or assigned.
WARNING:Xst:1780 - Signal <dio_output_06> is never used or assigned.
WARNING:Xst:1780 - Signal <dio_output_11> is never used or assigned.
WARNING:Xst:1780 - Signal <dio_enable_indiv_02> is never used or assigned.
WARNING:Xst:1780 - Signal <dio_output_07> is never used or assigned.
WARNING:Xst:1780 - Signal <dio_output_12> is never used or assigned.
WARNING:Xst:1780 - Signal <dio_enable_indiv_03> is never used or assigned.
WARNING:Xst:1780 - Signal <dio_output_08> is never used or assigned.
WARNING:Xst:1780 - Signal <dio_output_13> is never used or assigned.
WARNING:Xst:1780 - Signal <dio_enable_indiv_04> is never used or assigned.
WARNING:Xst:1780 - Signal <dio_output_09> is never used or assigned.
WARNING:Xst:1780 - Signal <dio_output_14> is never used or assigned.
WARNING:Xst:1780 - Signal <dio_enable_indiv_05> is never used or assigned.
WARNING:Xst:1780 - Signal <dio_enable_indiv_10> is never used or assigned.
WARNING:Xst:1780 - Signal <dio_output_15> is never used or assigned.
WARNING:Xst:1780 - Signal <dio_output_20> is never used or assigned.
WARNING:Xst:1780 - Signal <dio_enable_indiv_06> is never used or assigned.
WARNING:Xst:1780 - Signal <dio_enable_indiv_11> is never used or assigned.
WARNING:Xst:1780 - Signal <dio_output_16> is never used or assigned.
WARNING:Xst:1780 - Signal <dio_output_21> is never used or assigned.
WARNING:Xst:1780 - Signal <dio_enable_indiv_07> is never used or assigned.
WARNING:Xst:1780 - Signal <dio_enable_indiv_12> is never used or assigned.
WARNING:Xst:1780 - Signal <dio_output_17> is never used or assigned.
WARNING:Xst:1780 - Signal <dio_output_22> is never used or assigned.
WARNING:Xst:1780 - Signal <dio_enable_indiv_08> is never used or assigned.
WARNING:Xst:1780 - Signal <dio_enable_indiv_13> is never used or assigned.
WARNING:Xst:1780 - Signal <dio_output_18> is never used or assigned.
WARNING:Xst:1780 - Signal <dio_output_23> is never used or assigned.
WARNING:Xst:1780 - Signal <dio_enable_indiv_09> is never used or assigned.
WARNING:Xst:1780 - Signal <dio_enable_indiv_14> is never used or assigned.
WARNING:Xst:1780 - Signal <dio_output_19> is never used or assigned.
WARNING:Xst:1780 - Signal <dio_output_24> is never used or assigned.
WARNING:Xst:1780 - Signal <dio_enable_indiv_15> is never used or assigned.
WARNING:Xst:1780 - Signal <dio_enable_indiv_20> is never used or assigned.
WARNING:Xst:1780 - Signal <dio_output_25> is never used or assigned.
WARNING:Xst:1780 - Signal <dio_output_30> is never used or assigned.
WARNING:Xst:1780 - Signal <dio_enable_indiv_16> is never used or assigned.
WARNING:Xst:1780 - Signal <dio_enable_indiv_21> is never used or assigned.
WARNING:Xst:1780 - Signal <dio_output_26> is never used or assigned.
WARNING:Xst:1780 - Signal <dio_output_31> is never used or assigned.
WARNING:Xst:1780 - Signal <dio_enable_indiv_17> is never used or assigned.
WARNING:Xst:1780 - Signal <dio_enable_indiv_22> is never used or assigned.
WARNING:Xst:1780 - Signal <dio_output_27> is never used or assigned.
WARNING:Xst:1780 - Signal <dio_output_32> is never used or assigned.
WARNING:Xst:1780 - Signal <dio_enable_indiv_18> is never used or assigned.
WARNING:Xst:1780 - Signal <dio_enable_indiv_23> is never used or assigned.
WARNING:Xst:1780 - Signal <dio_output_28> is never used or assigned.
WARNING:Xst:1780 - Signal <dio_output_33> is never used or assigned.
WARNING:Xst:1780 - Signal <dio_enable_indiv_19> is never used or assigned.
WARNING:Xst:1780 - Signal <dio_enable_indiv_24> is never used or assigned.
WARNING:Xst:1780 - Signal <dio_output_29> is never used or assigned.
WARNING:Xst:1780 - Signal <dio_output_34> is never used or assigned.
WARNING:Xst:1780 - Signal <dio_enable_indiv_25> is never used or assigned.
WARNING:Xst:1780 - Signal <dio_enable_indiv_30> is never used or assigned.
WARNING:Xst:1780 - Signal <dio_output_35> is never used or assigned.
WARNING:Xst:1780 - Signal <dio_output_40> is never used or assigned.
WARNING:Xst:1780 - Signal <dio_enable_indiv_26> is never used or assigned.
WARNING:Xst:1780 - Signal <dio_enable_indiv_31> is never used or assigned.
WARNING:Xst:1780 - Signal <dio_output_36> is never used or assigned.
WARNING:Xst:1780 - Signal <dio_output_41> is never used or assigned.
WARNING:Xst:1780 - Signal <dio_enable_indiv_27> is never used or assigned.
WARNING:Xst:1780 - Signal <dio_enable_indiv_32> is never used or assigned.
WARNING:Xst:1780 - Signal <dio_output_37> is never used or assigned.
WARNING:Xst:1780 - Signal <dio_output_42> is never used or assigned.
WARNING:Xst:1780 - Signal <dio_enable_indiv_28> is never used or assigned.
WARNING:Xst:1780 - Signal <dio_enable_indiv_33> is never used or assigned.
WARNING:Xst:1780 - Signal <dio_output_38> is never used or assigned.
WARNING:Xst:1780 - Signal <dio_output_43> is never used or assigned.
WARNING:Xst:1780 - Signal <dio_enable_indiv_29> is never used or assigned.
WARNING:Xst:1780 - Signal <dio_enable_indiv_34> is never used or assigned.
WARNING:Xst:1780 - Signal <dio_output_39> is never used or assigned.
WARNING:Xst:1780 - Signal <dio_output_44> is never used or assigned.
WARNING:Xst:1780 - Signal <dio_enable_indiv_35> is never used or assigned.
WARNING:Xst:1780 - Signal <dio_enable_indiv_40> is never used or assigned.
WARNING:Xst:1780 - Signal <dio_output_50> is never used or assigned.
WARNING:Xst:1780 - Signal <dio_output_45> is never used or assigned.
WARNING:Xst:1780 - Signal <dio_enable_indiv_36> is never used or assigned.
WARNING:Xst:1780 - Signal <dio_enable_indiv_41> is never used or assigned.
WARNING:Xst:1780 - Signal <dio_output_51> is never used or assigned.
WARNING:Xst:1780 - Signal <dio_output_46> is never used or assigned.
WARNING:Xst:1780 - Signal <dio_enable_indiv_37> is never used or assigned.
WARNING:Xst:1780 - Signal <dio_enable_indiv_42> is never used or assigned.
WARNING:Xst:1780 - Signal <dio_output_52> is never used or assigned.
WARNING:Xst:1780 - Signal <dio_output_47> is never used or assigned.
WARNING:Xst:1780 - Signal <dio_enable_indiv_38> is never used or assigned.
WARNING:Xst:1780 - Signal <dio_enable_indiv_43> is never used or assigned.
WARNING:Xst:1780 - Signal <dio_output_53> is never used or assigned.
WARNING:Xst:1780 - Signal <dio_output_48> is never used or assigned.
WARNING:Xst:1780 - Signal <dio_enable_indiv_39> is never used or assigned.
WARNING:Xst:1780 - Signal <dio_enable_indiv_44> is never used or assigned.
WARNING:Xst:1780 - Signal <dio_output_54> is never used or assigned.
WARNING:Xst:1780 - Signal <dio_enable_indiv_50> is never used or assigned.
WARNING:Xst:1780 - Signal <dio_output_49> is never used or assigned.
WARNING:Xst:1780 - Signal <dio_enable_indiv_45> is never used or assigned.
WARNING:Xst:1780 - Signal <dio_output_60> is never used or assigned.
WARNING:Xst:1780 - Signal <dio_output_55> is never used or assigned.
WARNING:Xst:1780 - Signal <dio_enable_indiv_51> is never used or assigned.
WARNING:Xst:1780 - Signal <dio_enable_indiv_46> is never used or assigned.
WARNING:Xst:1780 - Signal <dio_output_61> is never used or assigned.
WARNING:Xst:1780 - Signal <dio_output_56> is never used or assigned.
WARNING:Xst:1780 - Signal <dio_enable_indiv_52> is never used or assigned.
WARNING:Xst:1780 - Signal <dio_enable_indiv_47> is never used or assigned.
WARNING:Xst:1780 - Signal <dio_output_62> is never used or assigned.
WARNING:Xst:1780 - Signal <dio_output_57> is never used or assigned.
WARNING:Xst:1780 - Signal <dio_enable_indiv_53> is never used or assigned.
WARNING:Xst:1780 - Signal <dio_enable_indiv_48> is never used or assigned.
WARNING:Xst:1780 - Signal <dio_output_63> is never used or assigned.
WARNING:Xst:1780 - Signal <dio_output_58> is never used or assigned.
WARNING:Xst:1780 - Signal <dio_enable_indiv_54> is never used or assigned.
WARNING:Xst:1780 - Signal <dio_enable_indiv_49> is never used or assigned.
WARNING:Xst:1780 - Signal <dio_output_64> is never used or assigned.
WARNING:Xst:1780 - Signal <dio_enable_indiv_60> is never used or assigned.
WARNING:Xst:1780 - Signal <dio_output_59> is never used or assigned.
WARNING:Xst:1780 - Signal <dio_enable_indiv_55> is never used or assigned.
WARNING:Xst:1780 - Signal <dio_output_70> is never used or assigned.
WARNING:Xst:1780 - Signal <dio_output_65> is never used or assigned.
WARNING:Xst:1780 - Signal <dio_enable_indiv_61> is never used or assigned.
WARNING:Xst:1780 - Signal <dio_enable_indiv_56> is never used or assigned.
WARNING:Xst:1780 - Signal <dio_output_71> is never used or assigned.
WARNING:Xst:1780 - Signal <dio_output_66> is never used or assigned.
WARNING:Xst:1780 - Signal <dio_enable_indiv_62> is never used or assigned.
WARNING:Xst:1780 - Signal <dio_enable_indiv_57> is never used or assigned.
WARNING:Xst:1780 - Signal <dio_output_72> is never used or assigned.
WARNING:Xst:1780 - Signal <dio_output_67> is never used or assigned.
WARNING:Xst:1780 - Signal <dio_enable_indiv_63> is never used or assigned.
WARNING:Xst:1780 - Signal <dio_enable_indiv_58> is never used or assigned.
WARNING:Xst:1780 - Signal <dio_output_73> is never used or assigned.
WARNING:Xst:1780 - Signal <dio_output_68> is never used or assigned.
WARNING:Xst:1780 - Signal <dio_enable_indiv_64> is never used or assigned.
WARNING:Xst:1780 - Signal <dio_enable_indiv_59> is never used or assigned.
WARNING:Xst:1780 - Signal <dio_output_74> is never used or assigned.
WARNING:Xst:1780 - Signal <dio_enable_indiv_70> is never used or assigned.
WARNING:Xst:1780 - Signal <dio_output_69> is never used or assigned.
WARNING:Xst:1780 - Signal <dio_enable_indiv_65> is never used or assigned.
WARNING:Xst:1780 - Signal <dio_output_75> is never used or assigned.
WARNING:Xst:1780 - Signal <dio_enable_indiv_71> is never used or assigned.
WARNING:Xst:1780 - Signal <dio_enable_indiv_66> is never used or assigned.
WARNING:Xst:1780 - Signal <dio_output_76> is never used or assigned.
WARNING:Xst:1780 - Signal <dio_enable_indiv_72> is never used or assigned.
WARNING:Xst:1780 - Signal <dio_enable_indiv_67> is never used or assigned.
WARNING:Xst:1780 - Signal <dio_output_77> is never used or assigned.
WARNING:Xst:1780 - Signal <dio_enable_indiv_73> is never used or assigned.
WARNING:Xst:1780 - Signal <dio_enable_indiv_68> is never used or assigned.
WARNING:Xst:1780 - Signal <dio_output_78> is never used or assigned.
WARNING:Xst:1780 - Signal <dio_enable_indiv_74> is never used or assigned.
WARNING:Xst:1780 - Signal <dio_enable_indiv_69> is never used or assigned.
WARNING:Xst:1780 - Signal <dio_output_79> is never used or assigned.
WARNING:Xst:1780 - Signal <dio_enable_indiv_75> is never used or assigned.
WARNING:Xst:1780 - Signal <dio_enable_indiv_76> is never used or assigned.
WARNING:Xst:1780 - Signal <dio_enable_indiv_77> is never used or assigned.
WARNING:Xst:1780 - Signal <dio_enable_indiv_78> is never used or assigned.
WARNING:Xst:1780 - Signal <dio_enable_indiv_79> is never used or assigned.
WARNING:Xst:1780 - Signal <ctrl_clr> is never used or assigned.
WARNING:Xst:1780 - Signal <mIoDataOutEnable> is never used or assigned.
WARNING:Xst:1780 - Signal <iodtk_n_all> is never used or assigned.
WARNING:Xst:1780 - Signal <CPU_temperature_miso> is never used or assigned.
    Found 1-bit tristate buffer for signal <iordy>.
    Found 1-bit tristate buffer for signal <system_reset_n>.
    Found 32-bit tristate buffer for signal <d>.
    Found 1-bit register for signal <aDiagramReset>.
    Summary:
	inferred   1 D-type flip-flop(s).
	inferred  34 Tristate(s).
Unit <toplevel_gen> synthesized.

WARNING:Xst:524 - All outputs of the instance <enableDelayer> of the block <nirvi_ZeroDelayer> are unconnected in block <cpdarith_0031>.
   This instance will be removed from the design along with all underlying logic

=========================================================================
HDL Synthesis Report

Macro Statistics
# Counters                                             : 2
 16-bit up counter                                     : 1
 4-bit down counter                                    : 1
# Registers                                            : 237
 1-bit register                                        : 225
 13-bit register                                       : 1
 32-bit register                                       : 7
 35-bit register                                       : 2
 5-bit register                                        : 2
# Comparators                                          : 2
 13-bit comparator greatequal                          : 1
 13-bit comparator less                                : 1
# Tristates                                            : 4
 1-bit tristate buffer                                 : 3
 32-bit tristate buffer                                : 1
# Xors                                                 : 8
 1-bit xor2                                            : 8

=========================================================================

=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Analyzing FSM <FSM_3> for best encoding.
Optimizing FSM <mytop/n_145/MiteInterfacex/RegisterAccessx/RegisterAccess32x/mReadState> on signal <mReadState[1:2]> with gray encoding.
---------------------
 State   | Encoding
---------------------
 idle    | 00
 reading | 01
 done    | 11
---------------------
Analyzing FSM <FSM_2> for best encoding.
Optimizing FSM <mytop/n_145/MiteInterfacex/RegisterAccessx/RegisterAccess32x/mWriteState> on signal <mWriteState[1:2]> with gray encoding.
---------------------
 State   | Encoding
---------------------
 idle    | 00
 writing | 01
 done    | 11
---------------------
Analyzing FSM <FSM_1> for best encoding.
Optimizing FSM <mytop/n_145/MiteInterfacex/MiteInterfaceOutputEnables/mAccessType0> on signal <mAccessType0[1:2]> with speed1 encoding.
----------------------
 State    | Encoding
----------------------
 dma      | 00
 regular  | 10
 noaccess | 01
----------------------
Analyzing FSM <FSM_0> for best encoding.
Optimizing FSM <mytop/n_145/MiteInterfacex/MiteInterfaceOutputEnables/mAccessType> on signal <mAccessType[1:2]> with sequential encoding.
--------------------------
 State        | Encoding
--------------------------
 dmaread      | 00
 stopdmaread  | 11
 registerread | 10
 notreading   | 01
--------------------------
Loading device for application Rf_Device from file '3s2000.nph' in environment C:\NIFPGA85\Xilinx.
WARNING:Xst:1290 - Hierarchical block <n_132> is unconnected in block <nSCTL_L45814900_17_138>.
   It will be removed from the design.
WARNING:Xst:1290 - Hierarchical block <n_133> is unconnected in block <nSCTL_L45814900_17_138>.
   It will be removed from the design.
WARNING:Xst:1290 - Hierarchical block <n_134> is unconnected in block <n_135>.
   It will be removed from the design.
WARNING:Xst:1290 - Hierarchical block <n_143> is unconnected in block <mytop>.
   It will be removed from the design.
WARNING:Xst:1290 - Hierarchical block <HandShakeIrqAck> is unconnected in block <IrqComponents[0].MiteIrqx>.
   It will be removed from the design.
WARNING:Xst:1290 - Hierarchical block <n_150> is unconnected in block <mytop>.
   It will be removed from the design.
WARNING:Xst:1290 - Hierarchical block <cop_0_0> is unconnected in block <n_131>.
   It will be removed from the design.
WARNING:Xst:1290 - Hierarchical block <cop_0_1> is unconnected in block <n_131>.
   It will be removed from the design.
WARNING:Xst:1290 - Hierarchical block <cop_0_2> is unconnected in block <n_131>.
   It will be removed from the design.
WARNING:Xst:1290 - Hierarchical block <cop_0_3> is unconnected in block <n_131>.
   It will be removed from the design.
WARNING:Xst:1290 - Hierarchical block <cop_1_0> is unconnected in block <n_131>.
   It will be removed from the design.
WARNING:Xst:1290 - Hierarchical block <cop_1_1> is unconnected in block <n_131>.
   It will be removed from the design.
WARNING:Xst:1290 - Hierarchical block <cop_2_0> is unconnected in block <n_131>.
   It will be removed from the design.
WARNING:Xst:1290 - Hierarchical block <HandShakeIrqNum> is unconnected in block <IrqComponents[0].MiteIrqx>.
   It will be removed from the design.

=========================================================================
Advanced HDL Synthesis Report

Macro Statistics
# FSMs                                                 : 4
# Counters                                             : 2
 16-bit up counter                                     : 1
 4-bit down counter                                    : 1
# Registers                                            : 549
 Flip-Flops                                            : 549
# Comparators                                          : 2
 13-bit comparator greatequal                          : 1
 13-bit comparator less                                : 1
# Xors                                                 : 8
 1-bit xor2                                            : 8

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================

Optimizing unit <toplevel_gen> ...

Optimizing unit <ShiftRegComp> ...

Optimizing unit <HandshakeBase_1> ...

Optimizing unit <HandshakeBase_2> ...

Optimizing unit <RegisterAccess32> ...

Optimizing unit <HandshakeBase_3> ...

Optimizing unit <bushold> ...

Optimizing unit <MiteIrq> ...

Mapping all equations...
Building and optimizing final netlist ...

Final Macro Processing ...

Processing Unit <toplevel_gen> :
INFO:Xst:741 - HDL ADVISOR - A 2-bit shift register was found for signal <mytop/n_146/iEnableOut> and currently occupies 2 logic cells (1 slices). Removing the set/reset logic would take advantage of SRL16 (and derived) primitives and reduce this to 1 logic cells (1 slices). Evaluate if the set/reset can be removed for this simple shift register. The majority of simple pipeline structures do not need to be set/reset operationally.
INFO:Xst:741 - HDL ADVISOR - A 2-bit shift register was found for signal <mytop/n_146/tDiagramEnableIn> and currently occupies 2 logic cells (1 slices). Removing the set/reset logic would take advantage of SRL16 (and derived) primitives and reduce this to 1 logic cells (1 slices). Evaluate if the set/reset can be removed for this simple shift register. The majority of simple pipeline structures do not need to be set/reset operationally.
INFO:Xst:741 - HDL ADVISOR - A 2-bit shift register was found for signal <mytop/n_146/tDiagramEnableClear> and currently occupies 2 logic cells (1 slices). Removing the set/reset logic would take advantage of SRL16 (and derived) primitives and reduce this to 1 logic cells (1 slices). Evaluate if the set/reset can be removed for this simple shift register. The majority of simple pipeline structures do not need to be set/reset operationally.
INFO:Xst:741 - HDL ADVISOR - A 2-bit shift register was found for signal <mytop/n_144/Clk40Crossing.Clk40ToInterface/HBx/oPushToggle1_0> and currently occupies 2 logic cells (1 slices). Removing the set/reset logic would take advantage of SRL16 (and derived) primitives and reduce this to 1 logic cells (1 slices). Evaluate if the set/reset can be removed for this simple shift register. The majority of simple pipeline structures do not need to be set/reset operationally.
INFO:Xst:741 - HDL ADVISOR - A 2-bit shift register was found for signal <mytop/n_144/Clk40Crossing.Clk40FromInterface/HBx/iReset_0> and currently occupies 2 logic cells (1 slices). Removing the set/reset logic would take advantage of SRL16 (and derived) primitives and reduce this to 1 logic cells (1 slices). Evaluate if the set/reset can be removed for this simple shift register. The majority of simple pipeline structures do not need to be set/reset operationally.
INFO:Xst:741 - HDL ADVISOR - A 2-bit shift register was found for signal <mytop/n_144/Clk40Crossing.Clk40FromInterface/HBx/oPushToggle1_0> and currently occupies 2 logic cells (1 slices). Removing the set/reset logic would take advantage of SRL16 (and derived) primitives and reduce this to 1 logic cells (1 slices). Evaluate if the set/reset can be removed for this simple shift register. The majority of simple pipeline structures do not need to be set/reset operationally.
INFO:Xst:741 - HDL ADVISOR - A 2-bit shift register was found for signal <mytop/n_144/Clk40Crossing.Clk40FromInterface/HBx/iRdyPushToggle_0> and currently occupies 2 logic cells (1 slices). Removing the set/reset logic would take advantage of SRL16 (and derived) primitives and reduce this to 1 logic cells (1 slices). Evaluate if the set/reset can be removed for this simple shift register. The majority of simple pipeline structures do not need to be set/reset operationally.
INFO:Xst:741 - HDL ADVISOR - A 2-bit shift register was found for signal <mytop/n_144/MiteClkShifter.ShiftRegister/cDelayedWritePulse2_0> and currently occupies 2 logic cells (1 slices). Removing the set/reset logic would take advantage of SRL16 (and derived) primitives and reduce this to 1 logic cells (1 slices). Evaluate if the set/reset can be removed for this simple shift register. The majority of simple pipeline structures do not need to be set/reset operationally.
Unit <toplevel_gen> processed.

=========================================================================
Final Register Report

Macro Statistics
# Registers                                            : 293
 Flip-Flops                                            : 293

=========================================================================

=========================================================================
*                          Partition Report                             *
=========================================================================

Partition Implementation Status
-------------------------------

  No Partitions were found in this design.

-------------------------------

=========================================================================
*                            Final Report                               *
=========================================================================
Final Results
RTL Top Level Output File Name     : toplevel_gen.ngr
Top Level Output File Name         : toplevel_gen
Output Format                      : ngc
Optimization Goal                  : SPEED
Keep Hierarchy                     : no

Design Statistics
# IOs                              : 243

Cell Usage :
# BELS                             : 372
#      GND                         : 1
#      INV                         : 8
#      LUT1                        : 18
#      LUT2                        : 41
#      LUT2_L                      : 2
#      LUT3                        : 68
#      LUT3_L                      : 2
#      LUT4                        : 156
#      LUT4_D                      : 8
#      LUT4_L                      : 22
#      MUXCY                       : 25
#      MUXF5                       : 5
#      VCC                         : 1
#      XORCY                       : 15
# FlipFlops/Latches                : 293
#      FD                          : 1
#      FDC                         : 84
#      FDCE                        : 201
#      FDP                         : 6
#      FDRE                        : 1
# Clock Buffers                    : 2
#      BUFG                        : 1
#      BUFGP                       : 1
# IO Buffers                       : 156
#      IBUF                        : 22
#      IBUFG                       : 1
#      IOBUF                       : 32
#      OBUF                        : 98
#      OBUFT                       : 3
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 3s2000fg456-4 

 Number of Slices:                     214  out of  20480     1%  
 Number of Slice Flip Flops:           293  out of  40960     0%  
 Number of 4 input LUTs:               325  out of  40960     0%  
 Number of IOs:                        243
 Number of bonded IOBs:                157  out of    333    47%  
 Number of GCLKs:                        2  out of      8    25%  

---------------------------
Partition Resource Summary:
---------------------------

  No Partitions were found in this design.

---------------------------


=========================================================================
TIMING REPORT

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
      FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
      GENERATED AFTER PLACE-and-ROUTE.

Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
MiteClk                            | BUFGP                  | 269   |
Clk40                              | IBUFG+BUFG             | 24    |
-----------------------------------+------------------------+-------+

Asynchronous Control Signals Information:
----------------------------------------
---------------------------------------------------------------------+-------------------------------------------------------------------------+-------+
Control Signal                                                       | Buffer(FF name)                                                         | Load  |
---------------------------------------------------------------------+-------------------------------------------------------------------------+-------+
aDiagramReset(aDiagramReset:Q)                                       | NONE(mytop/n_145/MiteInterfacex/IrqComponents[0].MiteIrqx/mMaskReg_14)  | 186   |
mytop/n_145/not0000_0_not0000(mytop/n_145/not0000_0_not00001_INV_0:O)| NONE(mytop/n_145/MiteInterfacex/RegisterAccessx/RegisterAccess32x/mQ_27)| 105   |
---------------------------------------------------------------------+-------------------------------------------------------------------------+-------+

Timing Summary:
---------------
Speed Grade: -4

   Minimum period: 8.293ns (Maximum Frequency: 120.584MHz)
   Minimum input arrival time before clock: 13.435ns
   Maximum output required time after clock: 9.812ns
   Maximum combinational path delay: No path found

Timing Detail:
--------------
All values displayed in nanoseconds (ns)

=========================================================================
Timing constraint: Default period analysis for Clock 'MiteClk'
  Clock period: 8.293ns (frequency: 120.584MHz)
  Total number of paths / destination ports: 6320 / 407
-------------------------------------------------------------------------
Delay:               8.293ns (Levels of Logic = 8)
  Source:            mytop/n_145/MiteInterfacex/RegisterAccessx/RegisterAccess32x/mRegPortIn.Address_0 (FF)
  Destination:       mytop/n_144/Clk40Crossing.Clk40FromInterface/HBx/iLclStoredData_0 (FF)
  Source Clock:      MiteClk rising
  Destination Clock: MiteClk rising

  Data Path: mytop/n_145/MiteInterfacex/RegisterAccessx/RegisterAccess32x/mRegPortIn.Address_0 to mytop/n_144/Clk40Crossing.Clk40FromInterface/HBx/iLclStoredData_0
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDC:C->Q             10   0.720   1.473  mytop/n_145/MiteInterfacex/RegisterAccessx/RegisterAccess32x/mRegPortIn.Address_0 (mytop/n_145/MiteInterfacex/RegisterAccessx/RegisterAccess32x/mRegPortIn.Address_0)
     LUT2:I0->O            1   0.551   0.000  mytop/n_144/Mcompar_iPush_0_cmp_lt0000_lut<0> (mytop/n_144/N7)
     MUXCY:S->O            1   0.500   0.000  mytop/n_144/Mcompar_iPush_0_cmp_lt0000_cy<0>_0 (mytop/n_144/Mcompar_iPush_0_cmp_lt0000_cy<0>1)
     MUXCY:CI->O           1   0.064   0.000  mytop/n_144/Mcompar_iPush_0_cmp_lt0000_cy<1>_0 (mytop/n_144/Mcompar_iPush_0_cmp_lt0000_cy<1>1)
     MUXCY:CI->O           1   0.064   0.000  mytop/n_144/Mcompar_iPush_0_cmp_lt0000_cy<2>_0 (mytop/n_144/Mcompar_iPush_0_cmp_lt0000_cy<2>1)
     MUXCY:CI->O           1   0.064   0.000  mytop/n_144/Mcompar_iPush_0_cmp_lt0000_cy<3>_0 (mytop/n_144/Mcompar_iPush_0_cmp_lt0000_cy<3>1)
     MUXCY:CI->O           1   0.303   0.827  mytop/n_144/Mcompar_iPush_0_cmp_lt0000_cy<4>_0 (mytop/n_144/iPush_0_cmp_ge0000)
     LUT4:I3->O            3   0.551   1.102  mytop/n_144/iPush_0_and00001 (mytop/n_144/iPush)
     LUT2:I1->O            5   0.551   0.921  mytop/n_144/Clk40Crossing.Clk40FromInterface/HBx/iLclStoredData_and00001 (mytop/n_144/Clk40Crossing.Clk40FromInterface/HBx/iLclStoredData_and0000)
     FDCE:CE                   0.602          mytop/n_144/Clk40Crossing.Clk40FromInterface/HBx/iLclStoredData_0
    ----------------------------------------
    Total                      8.293ns (3.970ns logic, 4.323ns route)
                                       (47.9% logic, 52.1% route)

=========================================================================
Timing constraint: Default period analysis for Clock 'Clk40'
  Clock period: 5.619ns (frequency: 177.968MHz)
  Total number of paths / destination ports: 63 / 26
-------------------------------------------------------------------------
Delay:               5.619ns (Levels of Logic = 2)
  Source:            mytop/n_144/Clk40Crossing.Clk40FromInterface/HBx/oData_1 (FF)
  Destination:       mytop/n_144/Clk40Crossing.Clk40ToInterface/HBx/iLclStoredData_0 (FF)
  Source Clock:      Clk40 rising
  Destination Clock: Clk40 rising

  Data Path: mytop/n_144/Clk40Crossing.Clk40FromInterface/HBx/oData_1 to mytop/n_144/Clk40Crossing.Clk40ToInterface/HBx/iLclStoredData_0
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDCE:C->Q             2   0.720   1.216  mytop/n_144/Clk40Crossing.Clk40FromInterface/HBx/oData_1 (mytop/n_144/Clk40Crossing.Clk40FromInterface/HBx/oData_1)
     LUT4:I0->O            3   0.551   1.102  mytop/n_144/clk40ToRestestaviaFPGACompileCopy1result0HostRead_0_mux00001 (mytop/arb0b0cc8d8_wo<0>)
     LUT2:I1->O            2   0.551   0.877  mytop/n_144/Clk40Crossing.Clk40ToInterface/HBx/iLclStoredData_and00001 (mytop/n_144/Clk40Crossing.Clk40ToInterface/HBx/iLclStoredData_and0000)
     FDCE:CE                   0.602          mytop/n_144/Clk40Crossing.Clk40ToInterface/HBx/iLclStoredData_0
    ----------------------------------------
    Total                      5.619ns (2.424ns logic, 3.195ns route)
                                       (43.1% logic, 56.9% route)

=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'MiteClk'
  Total number of paths / destination ports: 2345 / 158
-------------------------------------------------------------------------
Offset:              13.435ns (Levels of Logic = 9)
  Source:            a<8> (PAD)
  Destination:       mytop/n_145/MiteInterfacex/RegisterAccessx/RegisterAccess32x/mReadState_FFd1 (FF)
  Destination Clock: MiteClk rising

  Data Path: a<8> to mytop/n_145/MiteInterfacex/RegisterAccessx/RegisterAccess32x/mReadState_FFd1
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O             3   0.821   1.246  a_8_IBUF (a_8_IBUF)
     LUT4:I0->O            1   0.551   1.140  aDiagramReset_cmp_eq000055 (aDiagramReset_cmp_eq0000_map24)
     LUT4:I0->O            1   0.551   0.827  aDiagramReset_cmp_eq000068_SW0 (N761)
     LUT4:I3->O            6   0.551   1.198  aDiagramReset_cmp_eq000068 (aDiagramReset_cmp_eq0000)
     LUT2:I1->O           21   0.551   1.710  mIoRd_n1 (mIoRd_n)
     LUT4:I1->O            3   0.551   1.246  mytop/n_145/MiteInterfacex/RegisterAccessx/RegisterAccess32x/mReadState_FFd1-In_SW1 (N593)
     LUT4:I0->O            1   0.551   0.000  mytop/n_145/MiteInterfacex/mRegPortOutInternal_DataValid_0_or00001_SW0_F (N755)
     MUXF5:I0->O           1   0.360   0.827  mytop/n_145/MiteInterfacex/mRegPortOutInternal_DataValid_0_or00001_SW0 (N678)
     LUT4:I3->O            1   0.551   0.000  mytop/n_145/MiteInterfacex/RegisterAccessx/RegisterAccess32x/mReadState_FFd1-In (mytop/n_145/MiteInterfacex/RegisterAccessx/RegisterAccess32x/mReadState_FFd1-In)
     FDC:D                     0.203          mytop/n_145/MiteInterfacex/RegisterAccessx/RegisterAccess32x/mReadState_FFd1
    ----------------------------------------
    Total                     13.435ns (5.241ns logic, 8.194ns route)
                                       (39.0% logic, 61.0% route)

=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'MiteClk'
  Total number of paths / destination ports: 67 / 33
-------------------------------------------------------------------------
Offset:              9.812ns (Levels of Logic = 2)
  Source:            mytop/n_145/MiteInterfacex/MiteInterfaceOutputEnables/mDataOE (FF)
  Destination:       d<31> (PAD)
  Source Clock:      MiteClk rising

  Data Path: mytop/n_145/MiteInterfacex/MiteInterfaceOutputEnables/mDataOE to d<31>
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDC:C->Q              1   0.720   0.801  mytop/n_145/MiteInterfacex/MiteInterfaceOutputEnables/mDataOE (mytop/n_145/MiteInterfacex/MiteInterfaceOutputEnables/mDataOE)
     INV:I->O             32   0.551   1.853  mDataOE_inv1_INV_0 (mDataOE_inv)
     IOBUF:T->IO               5.887          d_31_IOBUF (d<31>)
    ----------------------------------------
    Total                      9.812ns (7.158ns logic, 2.654ns route)
                                       (73.0% logic, 27.0% route)

=========================================================================
CPU : 114.40 / 114.46 s | Elapsed : 114.00 / 114.00 s
 
--> 

Total memory usage is 225516 kilobytes

Number of errors   :    0 (   0 filtered)
Number of warnings :  750 (   0 filtered)
Number of infos    :   90 (   0 filtered)