This document contains the LabVIEW NXG 3.0 FPGA Module known issues that were discovered before and since the release of LabVIEW NXG 3.0 FPGA Module. Not every issue known to NI will appear on this list; it is intended to only show the severe and more common issues that can be encountered.
Renaming an FPGA Application breaks associated Open FPGA VI Reference nodes referencing that application
Renaming an FPGA Application breaks associated Open FPGA VI Reference nodes referencing that application because the 'Rename and Update' dialog fails to automatically update the reference to use the new name.
Workaround: Manually point the Open FPGA VI Reference to the correct FPGA Application.
A VI that contains a Multirate Diagram created in LabVIEW Communications 2.1 does not compile
Any VI that contains a Multirate Diagram created in LabVIEW Communications 2.1 does not compile. Multirate Diagrams are only available in LabVIEW Communications and this issue occurs on machines with the LabVIEW NXG FPGA Module installed but without LabVIEW Communications installed.
Workaround: Install and activate LabVIEW Communications before opening the VI.
The LabVIEW FPGA Host Interface does not support reading or writing controls or indicators with Chinese characters
Attempting to read from or write to an FPGA control or indicator whose name contains Chinese characters from the LabVIEW FPGA Host Interface results in error -61206: "The configured item does not exist."
Workaround: Eliminate non-English characters from the names of controls and indicators.
Uninstalling the LabVIEW FPGA Compile Worker causes the LabVIEW NXG FPGA Compile Worker to fail.
Uninstalling the LabVIEW FPGA Compile Worker on machine with both the LabVIEW FPGA Compile Worker installed and the LabVIEW NXG FPGA Compile Worker installed causes the LabVIEW NXG FPGA Compile Worker to fail.
Workaround: Reinstall the LabVIEW NXG FPGA Compile Worker.
Reported Compile Duration may be incorrect after reconnecting to compilation.
If a disconnection and re-connection occurs during an FPGA compilation, then Total Duration and Compile Time information may be displayed incorrectly on the bitfile document.
Workaround: This issue only affects Total Duration and Compile Time displayed on the bitfile document. The elapsed time of each compile step is still correct and this issue does not affect functionality of the actual compilation process.