Because of the extremely high data rates of high-speed serial interfaces—with analog bandwidths exceeding 20 GHz—connectivity and cabling are critical. The PXIe-7902, PXIe-6591, and PXIe-6592 each provide distinct options to simplify connectivity for specific use cases. Apart from this, however, they are similar. All three modules feature Xilinx FPGAs at their core.
Figure 2. PXIe-7902 hardware architecture with key interfaces and data rates.
The Xilinx 7 Series GTX transceivers are the key technology behind these instruments. With up to 24 lanes at 12.5 Gbps, they offer a combined transmit and receive bandwidth of 600 Gbps and support a wide variety of serial protocols. They use current mode logic (CML), which is a differential interface that features a small signal swing of 800 mVpp (nominally, 1000 mVpp max.) for reduced power consumption and radiated emissions, and a 100 ohm differential (50 ohm per signal leg) impedance to minimize reflections and the resulting signal aberrations at high data rates. Additionally, for optimum signal fidelity these transceivers include a programmable transmit amplitude to compensate for long cables as well as transmit pre- and post-emphasis and auto-adaptive receiver equalization to overcome limited analog channel/cable bandwidth.
All high-speed serial interfaces require a reference clock that operates at an integer divisor of the line rate. For maximum flexibility, the GTX transceivers include a phase-locked loop (PLL) that can multiply the reference clock up to 100 times to produce the serial data rate. They also include serial-to-parallel and parallel-to-serial converters with ratios up to 80x, limiting FPGA clock frequencies while enabling high serial data rates. Furthermore, the transceivers have built-in 8b/10b, 64b/66b, and 64b/67b encoding and decoding structures to ensure a sufficient number of signal transitions for clock recovery, and to avoid consuming general-purpose FPGA resources. The Xilinx 7 Series FPGAs GTX/GTH Transceivers User Guide provides more details on Xilinx GTX transceivers.
In addition to providing the high-speed serial transceivers, the Xilinx FPGAs on the instruments serve a number of other vital purposes. They implement the logic for the protocol in use, as well as any application-specific user logic for hardware configuration and data generation, reception, and movement throughout the system. The XC7VX485T FPGA on the PXIe-7902 includes 303k LUTs, 2,800 DSP slices, and 37 Mb of block Ram, while the XC7K410T FPGA on the PXIe-6591 and PXIe-6592 includes 254k LUTs, 1,540 DSP slices, and 28 Mb of block RAM. Both FPGAs provide ample resources for a wide variety of high-performance applications. Directly connected to the FPGAs are 2 GB of onboard DDR3 DRAM that can be read from or written to at rates up to 10.6 GB/s (theoretical maximum) in user-defined access patterns. The FPGA also includes a PCI Express x8 Gen 2 interface to the PXI Express backplane for data streaming to and from host and disk, or P2P to other FPGA-enabled devices in the system at unidirectional rates up to 3.2 GB/s and bidirectional rates up to 2.4 GB/s in each direction (4.8 GB/s aggregate).
A low-jitter, high-fidelity reference clock is a critical component of any high-speed serial communications system. The PXIe-7902, PXIe-6591, and PXIe-6592 have an onboard, any-rate synthesizer for MGT operation over the full range of the Xilinx GTX transceivers, from 500 Mbps to 8 Gbps, and 9.8 Gbps to the maximum device rate. The PXIe-6591 and PXIe-6592 feature front panel coaxial connectivity for exporting the built-in reference clock, and all three modules have connectivity for importing an external reference clock. Finally, the devices can route the PXI Express 100 MHz or DStarA backplane clocks as a reference for the MGTs.
The PXIe-7902 High-Speed Serial Instrument
Figure 3. The PXIe-7902 High-Speed Serial Instrument with maximum 12.5 Gbps line rate and 24 TX and RX lines using a Mini-SAS HD connection.
The PXIe-7902 features six Mini-SAS HD (Molex iPass+ HD) connectors supporting rates up to 12.5 Gbps. Each connector includes four AC-coupled, differential TX and RX channels for a total of 24. Though designed for Serial-Attached SCSI (SAS), these connectors work with a variety of serial protocols and offer very high density. The module also includes an SMA connector for importing the MGT reference clock.
Electrical (copper) Mini-SAS HD cables are available in lengths up to three meters. Active optical cables (AOCs) are also available in lengths up to and beyond 100 meters. The PXIe-7902 provides electrical power to these cables per the Mini-SAS HD connector specification. The cables perform electrical-to-optical and optical-to-electrical conversion in the connector housing. Because these cables are factory-terminated, there are generally fewer length options when compared to other fiber-optic connectivity solutions. In addition, they cannot be terminated in the field.
The PXIe-6591 High-Speed Serial Instrument
Figure 4. The PXIe-6591 High-Speed Serial Instrument with maximum 12.5 Gbps line rate and 8 TX and RX lines using a Mini-SAS HD connection.
Similar to the PXIe-7902, the PXIe-6591 features two Mini-SAS HD (Molex iPass+ HD) connectors supporting rates up to 12.5 Gbps. Each connector includes four AC-coupled, differential TX and RX channels for a total of eight. These connectors work with a variety of serial protocols and offer very high density, which leaves room for other connectivity on the front panel of the module. This connectivity includes an SMA connector for importing or exporting the MGT reference clock, as well as a VHDCI connector for general-purpose I/O. The VHDCI connector includes 20 single-ended signals supporting 1.2, 1.5, 1.8, 2.5, and 3.3 Volt logic at rates up to 200 Mbps with per-line, per-cycle direction control. The user-programmable FPGA controls these signals to implement application-specific functionality.
The PXIe-6592 High-Speed Serial Instrument
Figure 5. The PXIe-6592 High-Speed Serial Instrument with maximum 10.3125 Gbps and 4 TX and RX line using a SFP+ connection.
The PXIe-6592 features four SFP+ connectors that support rates up to 10.3125 Gbps. Each connector includes a single differential TX and RX channel. SFP+ connectors are most commonly found on Ethernet, Fibre Channel, synchronous optical network (SONET), and optical transport network (OTN) interfaces. However, they may also carry other serial protocols. In addition, the NI PXIe-6592 includes four SMB connectors for general-purpose digital I/O and triggers, as well as MGT reference clock input and output. When configured for digital I/O, these signals are controlled by the user-programmable FPGA and implement 1.2, 1.5, 1.8, 2.5, and 3.3 Volts single-ended logic at rates up to 200 Mbps with per-line, per-cycle direction control.
The SFP+ connector scheme consists of a cage on the device or instrument and a transceiver module that resides in the cage. Optical transceiver modules are available for a variety of wavelengths of light, as well as single and multi-mode fibers. 1000BASE-T transceiver modules are also available for electrical (copper) Gigabit Ethernet applications. These, however, incorporate additional circuitry to convert to the pulse amplitude modulated signals used by Gigabit Ethernet. Finally, Direct Attach cables are available for direct, AC-coupled electrical connections in which the cable plugs directly into the SFP+ cage without a transceiver module.
An additional feature on the PXIe-6592 is a second, fixed reference clock at 156.25 MHz that engineers can use to implement two different serial protocols on the same device with different reference clock frequencies. A common example is the combination of one Gigabit Ethernet with the Common Public Radio Interface (CPRI) protocol, the former using the 156.25 MHz fixed clock and the latter using the any-rate clock synthesizer.
A software-designed instrument provides the same functionality as a fixed-function instrument, but users can customize the instrumentation hardware through an open, user-programmable FPGA. This level of customization is necessary in the PXI High-Speed Serial Instruments to support a variety of protocols and applications. As such, there is no single high-level API for programming these devices. Instead, they are programmed directly in LabVIEW software for both the host (CPU) and FPGA code, interfacing between the two with the lower level NI-RIO API. To help users get up and running quickly, a multitude of examples demonstrate the use of different protocols, as well as different use models for these instruments.
A software-designed instrument provides the same functionality as a fixed-function instrument, but users can customize the instrumentation hardware through an open, user-programmable FPGA
The open FPGA provides a degree of customization not found in other instruments. First and foremost, it implements the serial protocol for which the instrument is configured. This alone makes it possible for the PXIe-7902, PXIe-6591, and PXIe-6592 to support a multitude of standard and even custom serial protocols. Beyond just the protocol, user-defined hardware functionality allows types of tests not previously possible. For instance, algorithmic data generation on the FPGA reduces the required waveform storage memory and system bandwidth for downloading these waveforms, which accelerates test throughput. Algorithmic data analyses such as response comparison, intelligent triggering, and data reduction and compression drastically reduce the amount of data for the host CPU to process, which also decreases test time. User-defined DRAM access allows flexibility in how the DRAM is partitioned into stimulus and response regions. It also enables custom compression and decompression algorithms, which allows for optimal use of DRAM size and bandwidth. Standard waveform capture and playback is certainly possible, but depending on the protocol, line rate, and number of lanes, I/O bandwidth may exceed DRAM bandwidth. Finally, user-defined data movement to and from the PXIe-7902, PXIe-6591, or PXIe-6592 and the host or other instruments delivers significant flexibility for system-level integration. For example, it is possible to convert analog data to digital samples with a high-speed digitizer, use NI P2P streaming to transfer that data to a high-speed serial instrument at rates up to 3.2 GB/s, and then transmit those digital samples to an external device over a serial protocol. Alternatively, a high-speed serial instrument can capture a serial data stream and transfer it to the host CPU and ultimately a high-bandwidth RAID array for hours or even days of continuous storage, again at rates up to 3.2 GB/s.
LabVIEW FPGA makes it simple to configure and program these high-speed serial instruments. Figure 6 highlights the key interfaces accessible through LabVIEW, along with representative code. LabVIEW FPGA and the NI-RIO API provide efficient mechanisms for PCI Express-based data transfer between the host CPU and the FPGA, including register reads and writes as well as bi-directional DMA transfers. DRAM access—typically a challenging interface to manage in lower-level hardware description languages (HDLs) —is simplified through abstracted request, read, and write interfaces while maintaining high throughput and providing basic read/write arbitration. GTX transceiver configuration is generally protocol-specific and IP already exists for many high-speed serial interfaces (either HDL or netlist) with built-in transceiver configuration. This serial protocol interface is exposed in LabVIEW FPGA through a Socketed Component-Level IP (CLIP) interface. CLIP Nodes allow for the asynchronous operation of code not implemented in LabVIEW, but with a well-defined interface to the LabVIEW FPGA diagram. A common scenario uses Xlinx protocol-specific IP (including transceiver configuration) from the Xilinx Vivado IP Catalog and a thin layer of VHDL to define the interface to LabVIEW FPGA. After the protocol is implemented, LabVIEW FPGA offers a rich language for implementing arbitrary user logic such as decision-making, state machine implementation, DUT control, signal processing, and data movement.
Figure 6. LabVIEW FPGA provides graphical access to key aspects of the user-programmable FPGA on the PXIe-7902, PXIe-6591, and PXIe-6592.
Beyond defining the logic to be implemented on the user-programmable FPGA, LabVIEW simplifies hardware configuration through its project hierarchy and the associated configuration pages. For example, the reference clock configuration on these high-speed serial instruments requires a complex algorithm to determine hundreds of register settings to be applied to as many as four separate integrated circuits, in addition to the logic required to apply these registers when the FPGA powers on. LabVIEW FPGA exposes this as a dialog box with a graphical representation of the options, and design rules and guidance to enforce valid configurations. This simplifies the configuration of the any-rate clock synthesizer and routing circuitry to a task that takes minutes rather than hours or days.
Figure 7. LabVIEW FPGA delivers an intuitive, graphical interface for clock configuration that simplifies a complex process.
To enable code reuse and simplify common tasks, the PXIe-7902, PXIe-6591, and PXIe-6592 support certain instrument design libraries, which are host and FPGA code libraries with LabVIEW interfaces designed to work with one another and provide generic capabilities. The Instruction Framework is an instrument design library for dynamic hardware configuration during run time. Though most hardware functionality of these serial instruments (for example, clock configuration) can be statically configured in the LabVIEW project, users can take advantage of the Instruction Framework to control application-specific firmware parameters. For example, the Instruction Framework simplifies the host configuration of register settings exposed through AXI-4 Lite interfaces on the FPGA, commonly found in Xilinx serial protocol IP.
Figure 8. Processor and FPGA code for writing and reading registers through an AXI-4 Lite Interface
Built on top of the Instruction Framework, the Eye Scan instrument design library provides debug capabilities for the high-speed serial receive channels. The Xilinx GTX transceivers feature two receiver comparators per channel. While one comparator automatically tracks the center of the serial eye based on the recovered clock frequency and phase, the other comparator can independently shift in amplitude and phase. By varying the parameters of the latter comparator and comparing the results with that of the former, the Eye Scan instrument design library can create a statistical eye diagram useful for determining the link margin of the interface, accurate to the bit error rate floor of the Xilinx GTX transceivers. Furthermore, because the Eye Scan instrument design library uses an independent set of hardware resources, it can coexist with other protocol IP and run simultaneously with other application-specific functionality.
Figure 9. The LabVIEW Instrument Design Libraries for High Speed Serial Instruments includes a reference design for performing statistical eye scan using a loop-back configuration.
Beyond these instrument design libraries, other NI software-designed instruments provide libraries for a variety of useful functions such as multi-record, DRAM-based acquisition and generation. Though not officially supported or tested on the PXIe-7902, PXIe-6591, and PXIe-6592, depending on the hardware agnosticism of the instrument design library, they may be used with PXI High-Speed Serial Instruments as well.
Figure 10. Engineers can use the DSP instrument design library to synthesize a sinusoid for a transmission to a digital to analog converter over the serial JESD204B protocol.
NI provides a number of software examples to demonstrate how to integrate common protocols
The Xilinx GTX transceivers on the PXI High-Speed Serial Instruments support a broad variety of protocols. NI provides a number of software examples to demonstrate how to integrate common protocols, as well as LabVIEW architectures for several application patterns. Each example comes with a precompiled FPGA bitfile for the supported instrument, along with the associated source code and protocol IP. If this code requires modification for the end application, certain protocols require an IP license from Xilinx to recompile the FPGA. This protocol IP is available for purchase either through Xilinx or resellers such as Avnet or Digikey.
Xilinx Aurora provides a lightweight, low-latency, small-footprint protocol designed for serial point-to-point interfaces. It supports the full rate of the Xilinx GTX serial transceivers, as well as lane bonding for even greater bandwidth. Primarily designed for high-bandwidth data movement, Aurora provides flow control, flexible framing, and options for simplex or full-duplex channels. More information on Xilinx Aurora is at the following links:
The Instrument Design Libraries for High Speed Serial Instruments driver installs a sample project reference design for Aurora 64b66b, and NI has a web example for Aurora 8b10b.
As analog-to-digital converter (ADC) and digital-to-analog converter (DAC) sample rates and resolutions rise to meet the demands of wireless wideband modulated digital transmissions, data rates to and from these converters have increased. With traditional parallel clock and data interfaces, this calls for more integrated circuit pins with tighter tolerances. JESD204B meets this challenge by transitioning these interfaces to high-speed serial, which is designed to provide high data bandwidth with low latency and to facilitate multiconverter synchronization. JESD204B supports up to 12.5 Gbps and 32 lanes for the latest high-bandwidth, high-speed, and high-channel-count ADCs and DACs. More information on the Xilinx JESD204 IP core is at the following link:
This IP is available for purchase at Avnet or Digikey.
A reference design of JESD204B for the PXIe-6591 is on the NI Community.
10 Gigabit Ethernet
As networked computer traffic continues to rise, 10 Gigabit Ethernet will be the next dominant interface for short-range wired communications. With a line rate of 10.3125 Gbps, 10 Gigabit Ethernet provides a practical bandwidth of approximately 1 GB/s. Today, the majority of 10 Gigabit Ethernet interfaces are either optical or SFP+ Direct Attach (copper), with 8P8C/RJ45-based interfaces making up only a small, but growing fraction of the market. The 10 Gigabit Ethernet example for the PXIe-6592 supports 10GBASE-SR, -LR, and -ER optical interfaces as well as SFP+ Direct Attach, using the Xilinx 10 Gigabit Ethernet PCS/PMA IP core and the OpenCores.org 10 Gigabit Ethernet Media Access Controller. A lightweight UDP stack implemented in LabVIEW FPGA sits on top of this MAC/PHY solution. More information on 10 Gigabit Ethernet IP cores is at the following links:
The Instrument Design Libraries for High Speed Serial Instruments driver installs a sample project reference design for both 1 GbE and 10 GbE
CPRI defines the optical interface between the Radio Equipment Control (REC) and Radio Equipment (RE) commonly known as Remote Radio Heads (RRHs). It facilitates radio head configuration and synchronization, as well as streaming digital I/Q (baseband) data. More information on the Xilinx CPRI IP core is at the following link:
Serial RapidIO is a high-performance serial interconnect protocol optimized for energy-efficient embedded systems such as telecommunications infrastructure, military and aerospace embedded computing, high-bandwidth life sciences devices, and industrial control. It features rates up to 6.25 Gbps, four lane bonding, low latency, flow control, in-order packet delivery, and a relatively small footprint. More information on the Xilinx Serial RapidIO IP core is at the following link:
This IP is available for purchase at Avnet or Digikey.
A reference design of Serial RapidIO for the PXIe-6592 is on the NI Community.For SRIO interfaces larger than x2, NI recommends the PXIe-6591.
The above examples are not an exhaustive list of all protocols that are compatible with PXI High-Speed Serial Instruments. Local NI sales engineers can answer questions about specific protocols, customization of the above examples, or custom or proprietary protocol integration.