IP to FPGA Conversion Utility

To install the IP to FPGA Conversion Utility, refer to readme.

The IP to FPGA Conversion Utility has the following limitations:

• No support for double precision ports
• Only registers CPU-FPGA communication through Read/Write controls
• Only allows combinatorial circuits, such as circuits without clocks

Software Requirements

• MATLAB Simulink^® with HDL Coder license (r2020a or above)
• LabVIEW 2019/20 Full or Professional Development Systems (32-bit)
• LabVIEW 2019/20 FPGA Module (32-bit)
• NI R Series Multifunction RIO 20.0 LabVIEW 2019/20 Support (32-bit)

Steps

1. Open the model you want to convert into an NI FPGA bitfile in Simulink.
2. Navigate to the Configuration Parameters window.
   Note: For more information on the Simulink environment, refer to their documentation.
3. In the navigation pane, click HDL Coder Generation.
4. Set the Language to VHDL.
   Note: Verilog is not supported.
5. Set the Folder where Simulink will generate the VHDL code.
6. Click Run Compatibility Checker to confirm the compatibility of the model.
   
                                                        
   
   
7. In the navigation pane under HDL Code Generation, click Target and enter a Target Frequency (MHz).
   
                                                               
   
   
8. (Optional): If your model has an array or complex ports, in the navigation pane click Global Settings and set Scalarize ports to on.
   
                                                          
   
   
9. Save the model (.slx) and generate the HDL code.
10. Ensure that all LabVIEW and LabVIEW FPGA licenses are activated on the machine you are running the IP to FPGA Conversion Utility.
    Note: You can skip this step during subsequent bitfile conversions.
11. Open the Command Line and enter ip2fpgaCLI.exe.
12. Enter the create-config command to create a configurations template file.
    Note: For more information on the create-config command, refer to the Commands Table.
13. (Optional): To have the configuration template file map the model ports to Board I/Os, refer to Modifying Configuration Template File. By default, model ports map to registers.
14. Open LabVIEW and select the Compile Server option from Tools >> Options.
    Note: You can skip this step during subsequent bitfile conversions. For more information on compiling options, refer to NI LabVIEW FPGA Compilation Options.
    
                                                                           
    
    
15. Enter the build-bitfile command to generate the bitfile.
    Using this command causes the IP to FPGA Conversion Utility to display information in the command line output. This information includes the created LabVIEW Project Path, Data Ports table, Estimated Device Utilization, Final Device Utilization, Bitfile Path, and more.
    Note: For more information on build-bitfile command, refer to the Commands Table.

Software Requirements      

• VeriStand 2018 or above
• FPGA Addon Custom Device 20.6 or above

Steps

1. After generating a bitfile, import that file into VeriStand through the FPGA Addon Custom Device.
   The path to the bitfile can be found in the command line output.
   
   
   
   
2. Open VeriStand System Explorer to add the FPGA Addon Custom Device.
   Note: For more information, refer to the FPGA Addon Quick Start Guide on GitHub.

Interfacing with the Bitfile from other Applications

In addition to VeriStand, you can interface with the bitfile from the following applications:

• LabVIEW
• FPGA Interface C API

The configuration file allows the user to map a model port to the supported NI FPGA Board I/O or to registers. A template configuration file can be created by using the create-config command.

Note: By default, all model ports map to registers.

The configuration file also contains information on the available Board I/Os for the selected NI FPGA target. This helps with mapping model ports to Board I/Os.

Before modifying the configuration file, read the file’s Board I/O details. Understanding the direction and datatype of the model port and Board I/O is essential to determining the correct connection configuration. The following is a snippet of a model port mapped to a Board I/O.

Note: Using the build-bitfile command will trigger a data loss warning if the model port bitness does not match the mapped Board I/O bitness.

LabVIEW users may want to make the following changes:

• Add another custom IP
• Update the Xilinx Implementation Strategy
• Configure the Board I/O properties before generating a bitfile

To do so, open the LabVIEW project generated by the build-bitfile command using the command option -n:

ip2fpgaCLI.exe build-bitfile -p "C:\Users\SampleUser\Desktop\Sample\SubSystem.slx" -t "PXIe-7868R" -l 2019 -n

Use the generated LabVIEW project file to make the necessary modifications. You can find this file at the path displayed in the output window.