NI VeriStand 2018 Known Issues

Overview

This document contains the NI VeriStand 2018 known issues that were discovered before and since the release of NI VeriStand 2018. Not every issue known to NI will appear on this list; it is intended to only show the severe and more common issues that can be encountered.

Known Issues by Date

The following items are known issues in VeriStand 2018 sorted by Date.

317883 Using % in a block name causes a The MathWorks Inc. Simulink® model to fail to build
383092 Streaming a large number of waveform graphs can cause VeriStand gateway to stop responding
386381 The Pulse Measurement task may return incorrect data
392092 Error -200452 occurs when a 433x device uses hardware timed single point
402293 Model files imported to VeriStand with vector channels appear as Nx1 rather than 1xN
522678 Adding an FPGA target to the System Definition via the API will fail to add the Parameters section of PWM channels
372874 Building a LabVIEW model for NI VeriStand fails if the controls or indicators have identical names.
572887 Setting the Frame Type option in the Raw Data Frame Configuration page has no effect.
590854 Not possible to disable the VeriStand workspace
468712 VeriStand may select a DAQ card with Slow Background Conversion mode enabled as the chassis master timing device
669410 When no mappings are present, opening System Configuration Mappings may cause Error 1172.
672996 Frequency channels for Counter Inputs read an incorrectly scaled value.
676934 Boolean controls in VeriStand UI Manager do not have the Latch option as a Mechanical Action
689773 In VeriStand UI Manager, user channel data may not propagate to inactive Screens at launch



ID Known Issue
317883

Return
Using % in a block name causes a The MathWorks Inc. Simulink® model to fail to build
Using % in a block name causes a The MathWorks Inc. Simulink® model to fail to build

Workaround: Do not use % in the block name.

Reported Version: 2010    Resolved Version: N/A    Added: 10/09/2011
383092

Return
Streaming a large number of waveform graphs can cause VeriStand gateway to stop responding
Streaming a large number of waveforms to the waveform graph can cause the VeriStand gateway to be overwhelmed and stop responding in a timely fashion.

Workaround: Reduce CPU usage on the gateway computer or stream fewer waveforms.

Reported Version: 2012    Resolved Version: N/A    Added: 08/04/2014
386381

Return
The Pulse Measurement task may return incorrect data
In certain configurations where the signal is disconnected or has a 0/100% duty cycle, the Pulse Measurement task may report invalid readings. The returned reading of the disconnected signal will be the last non 0/100% duty cycle processed by your device.

Workaround: Install NI DAQmx 9.7 drivers

Reported Version: 2012    Resolved Version: N/A    Added: 08/04/2014
392092

Return
Error -200452 occurs when a 433x device uses hardware timed single point
If a 433x device is set as the master or if there is only a 433x device in a system definition, using hardware timed single point will cause error -200452 to occur during deployment.

Workaround: Use at least one other device in the system definition

Reported Version: 2012    Resolved Version: N/A    Added: 08/04/2014
402293

Return
Model files imported to VeriStand with vector channels appear as Nx1 rather than 1xN
Model files imported to VeriStand with vector channels appear as Nx1 rather than 1xN making it impossible to map to the channel correctly.

Workaround: Use the channel mappings dialog to import from a text file instead of using the dialog.

Reported Version: 2012    Resolved Version: N/A    Added: 08/04/2014
522678

Return
Adding an FPGA target to the System Definition via the API will fail to add the Parameters section of PWM channels
When using the System Definition API to programmatically add an FPGA target to a System Definition file, the Parameters section typically included with PWM channels is excluded.

Workaround: Add the FPGA manually to the System Definition via the System Explorer.

Reported Version: 2014    Resolved Version: N/A    Added: 08/13/2015
372874

Return
Building a LabVIEW model for NI VeriStand fails if the controls or indicators have identical names.
When building a VI into a model for NI VeriStand, the build process will fail if any of the indicators or controls have identical names.

Workaround: Use different names for the controls and indicators that will become the model's inports and outports.

Reported Version: 2011 SP1    Resolved Version: N/A    Added: 08/18/2015
572887

Return
Setting the Frame Type option in the Raw Data Frame Configuration page has no effect.
As the Frame Type is pulled from the XNET database, this System Definition setting does not affect the XNET configuration.

Workaround: Set the Frame Type as desired in the XNET database. Do not use the Raw Data Frame Type Configuration option in the System Definition.

Reported Version: 2014    Resolved Version: N/A    Added: 04/01/2016
590854

Return
Not possible to disable the VeriStand workspace
When UI Manager is used in a VeriStand project, both UI Manager and the Workspace are launched at execution time. There is currently no way to disable this.

Workaround: Launch your VeriStand project silently and then manually open UI Manager.

Reported Version: 2015 SP1    Resolved Version: N/A    Added: 06/08/2016
468712

Return
VeriStand may select a DAQ card with Slow Background Conversion mode enabled as the chassis master timing device
If Slow Background Conversion mode is enabled on a DAQ card (like a PXIe-4353) and it's the first DAQ device listed in the system definition, VeriStand incorrectly tries to use this device as the master timing card. VeriStand will do this even if there are other DAQ cards running without Slow Background Conversion enabled.

Workaround: Add the DAQ card that you want to use as the master timing source to the system definition before adding the Slow Background Conversion DAQ card. If both cads are already in the system definition, remove and re-add the Slow Background Conversion-enabled card.

Reported Version: 2013 SP1    Resolved Version: N/A    Added: 06/14/2017
669410

Return
When no mappings are present, opening System Configuration Mappings may cause Error 1172.
When no mappings are present in the System Configuration, the second attempt to open System Configuration Mappings for the VeriStand project will cause Error 1172.

Workaround: Close and re-open the current VeriStand project.

Reported Version: 2017    Resolved Version: N/A    Added: 07/02/2018
672996

Return
Frequency channels for Counter Inputs read an incorrectly scaled value.
The scaling on frequency channels with counter input modules is inaccurate. The channel value in VeriStand will depend on the number of frequency channels being read.

Workaround: A customer scale can be applied that reads the correct value. This scale should be: Channel Value / (Number of frequency channels + 1)

Reported Version: 2017    Resolved Version: N/A    Added: 07/02/2018
676934

Return
Boolean controls in VeriStand UI Manager do not have the Latch option as a Mechanical Action
VeriStand UI Manager boolean controls do not have the Latch Mechanical Action. Only the Switch Mechanical Action items can be selected.

Workaround: N/A

Reported Version: 2017    Resolved Version: Unknown    Added: 07/02/2018
689773

Return
In VeriStand UI Manager, user channel data may not propagate to inactive Screens at launch
When there are multiple screens present in VeriStand UI Manager, inactive screens may not propagate user channel data correctly. This occurs when the System Definition is deployed and starts running.

Workaround: Disconnect and reconnect VeriStand UI Manager from the running System Definition.

Reported Version: 2017    Resolved Version: Unknown    Added: 07/02/2018

Document last updated on 6/26/2018

Known Issues by Category

The following items are known issues in VeriStand 2018 sorted by Category.

Miscellaneous
386381 The Pulse Measurement task may return incorrect data
392092 Error -200452 occurs when a 433x device uses hardware timed single point
672996 Frequency channels for Counter Inputs read an incorrectly scaled value.
676934 Boolean controls in VeriStand UI Manager do not have the Latch option as a Mechanical Action
689773 In VeriStand UI Manager, user channel data may not propagate to inactive Screens at launch
Model Interfacing
317883 Using % in a block name causes a The MathWorks Inc. Simulink® model to fail to build
402293 Model files imported to VeriStand with vector channels appear as Nx1 rather than 1xN
372874 Building a LabVIEW model for NI VeriStand fails if the controls or indicators have identical names.
Performance
383092 Streaming a large number of waveform graphs can cause VeriStand gateway to stop responding
590854 Not possible to disable the VeriStand workspace
System Explorer
572887 Setting the Frame Type option in the Raw Data Frame Configuration page has no effect.
468712 VeriStand may select a DAQ card with Slow Background Conversion mode enabled as the chassis master timing device
669410 When no mappings are present, opening System Configuration Mappings may cause Error 1172.
Using the API
522678 Adding an FPGA target to the System Definition via the API will fail to add the Parameters section of PWM channels



ID Known Issue
Miscellaneous
386381

Return
The Pulse Measurement task may return incorrect data
In certain configurations where the signal is disconnected or has a 0/100% duty cycle, the Pulse Measurement task may report invalid readings. The returned reading of the disconnected signal will be the last non 0/100% duty cycle processed by your device.

Workaround: Install NI DAQmx 9.7 drivers

Reported Version: 2012    Resolved Version: N/A    Added: 08/04/2014
392092

Return
Error -200452 occurs when a 433x device uses hardware timed single point
If a 433x device is set as the master or if there is only a 433x device in a system definition, using hardware timed single point will cause error -200452 to occur during deployment.

Workaround: Use at least one other device in the system definition

Reported Version: 2012    Resolved Version: N/A    Added: 08/04/2014
672996

Return
Frequency channels for Counter Inputs read an incorrectly scaled value.
The scaling on frequency channels with counter input modules is inaccurate. The channel value in VeriStand will depend on the number of frequency channels being read.

Workaround: A customer scale can be applied that reads the correct value. This scale should be: Channel Value / (Number of frequency channels + 1)

Reported Version: 2017    Resolved Version: N/A    Added: 07/02/2018
676934

Return
Boolean controls in VeriStand UI Manager do not have the Latch option as a Mechanical Action
VeriStand UI Manager boolean controls do not have the Latch Mechanical Action. Only the Switch Mechanical Action items can be selected.

Workaround: N/A

Reported Version: 2017    Resolved Version: Unknown    Added: 07/02/2018
689773

Return
In VeriStand UI Manager, user channel data may not propagate to inactive Screens at launch
When there are multiple screens present in VeriStand UI Manager, inactive screens may not propagate user channel data correctly. This occurs when the System Definition is deployed and starts running.

Workaround: Disconnect and reconnect VeriStand UI Manager from the running System Definition.

Reported Version: 2017    Resolved Version: Unknown    Added: 07/02/2018
Model Interfacing
317883

Return
Using % in a block name causes a The MathWorks Inc. Simulink® model to fail to build
Using % in a block name causes a The MathWorks Inc. Simulink® model to fail to build

Workaround: Do not use % in the block name.

Reported Version: 2010    Resolved Version: N/A    Added: 10/09/2011
402293

Return
Model files imported to VeriStand with vector channels appear as Nx1 rather than 1xN
Model files imported to VeriStand with vector channels appear as Nx1 rather than 1xN making it impossible to map to the channel correctly.

Workaround: Use the channel mappings dialog to import from a text file instead of using the dialog.

Reported Version: 2012    Resolved Version: N/A    Added: 08/04/2014
372874

Return
Building a LabVIEW model for NI VeriStand fails if the controls or indicators have identical names.
When building a VI into a model for NI VeriStand, the build process will fail if any of the indicators or controls have identical names.

Workaround: Use different names for the controls and indicators that will become the model's inports and outports.

Reported Version: 2011 SP1    Resolved Version: N/A    Added: 08/18/2015
Performance
383092

Return
Streaming a large number of waveform graphs can cause VeriStand gateway to stop responding
Streaming a large number of waveforms to the waveform graph can cause the VeriStand gateway to be overwhelmed and stop responding in a timely fashion.

Workaround: Reduce CPU usage on the gateway computer or stream fewer waveforms.

Reported Version: 2012    Resolved Version: N/A    Added: 08/04/2014
590854

Return
Not possible to disable the VeriStand workspace
When UI Manager is used in a VeriStand project, both UI Manager and the Workspace are launched at execution time. There is currently no way to disable this.

Workaround: Launch your VeriStand project silently and then manually open UI Manager.

Reported Version: 2015 SP1    Resolved Version: N/A    Added: 06/08/2016
System Explorer
572887

Return
Setting the Frame Type option in the Raw Data Frame Configuration page has no effect.
As the Frame Type is pulled from the XNET database, this System Definition setting does not affect the XNET configuration.

Workaround: Set the Frame Type as desired in the XNET database. Do not use the Raw Data Frame Type Configuration option in the System Definition.

Reported Version: 2014    Resolved Version: N/A    Added: 04/01/2016
468712

Return
VeriStand may select a DAQ card with Slow Background Conversion mode enabled as the chassis master timing device
If Slow Background Conversion mode is enabled on a DAQ card (like a PXIe-4353) and it's the first DAQ device listed in the system definition, VeriStand incorrectly tries to use this device as the master timing card. VeriStand will do this even if there are other DAQ cards running without Slow Background Conversion enabled.

Workaround: Add the DAQ card that you want to use as the master timing source to the system definition before adding the Slow Background Conversion DAQ card. If both cads are already in the system definition, remove and re-add the Slow Background Conversion-enabled card.

Reported Version: 2013 SP1    Resolved Version: N/A    Added: 06/14/2017
669410

Return
When no mappings are present, opening System Configuration Mappings may cause Error 1172.
When no mappings are present in the System Configuration, the second attempt to open System Configuration Mappings for the VeriStand project will cause Error 1172.

Workaround: Close and re-open the current VeriStand project.

Reported Version: 2017    Resolved Version: N/A    Added: 07/02/2018
Using the API
522678

Return
Adding an FPGA target to the System Definition via the API will fail to add the Parameters section of PWM channels
When using the System Definition API to programmatically add an FPGA target to a System Definition file, the Parameters section typically included with PWM channels is excluded.

Workaround: Add the FPGA manually to the System Definition via the System Explorer.

Reported Version: 2014    Resolved Version: N/A    Added: 08/13/2015

Document last updated on 6/26/2018

Glossary of Terms

 

  • Bug ID - When an issue is reported to NI, you may be given this ID or find it on ni.com.  You may also find IDs posted by NI on the discussion forums or in KnowledgeBase articles.
  • Legacy ID – An older issue ID that refers to the same issue.  You may instead find this issue ID in older known issues documents.
  • Description - A few sentences which describe the problem. The brief description given does not necessarily describe the problem in full detail.
  • Workaround - Possible ways to work around the problem.
  • Reported Version - The earliest version in which the issue was reported.
  • Resolved Version - Version in which the issue was resolved or was no longer applicable. "N/A" indicates that the issue has not been resolved.
  • Date Added - The date the issue was added to the document (not the reported date).