LabVIEW 2017 and 2017 SP1 FPGA Module Known Issues

Overview

This document contains the LabVIEW 2017 and 2017 SP1 FPGA Module known issues that were discovered before and since the release of LabVIEW 2017 FPGA Module. Not every issue known to NI will appear on this list; it is intended to only show the severe and more common issues that can be encountered.

The LabVIEW 2017 Platform Known Issues contains a full listing of known issues, including LabVIEW toolkits and modules.

Known Issues by Date

The following items are known issues in LabVIEW 2017 and 2017 SP1 FPGA Module sorted by Date.

648682 The LabVIEW FPGA 2016 IP Builder will no longer function after upgrading the Xilinx Compilation Tool for Vivado 2015.4 that ships with the LabVIEW 2017 FPGA Module
629712 A crash can occur when adding an FPGA Handshake into a cluster
631368 A crash can occur if evaluating FPGA refnums from a static FPGA reference in simulation
640863 DMA channels are not available in the LabVIEW FPGA host interface if a DMA channel of type DBL is present
641409 Library incompatibility during installations of the Xilinx Compilation Tool for Vivado on Linux
669283 IP Integration Node saved in LabVIEW FPGA 2015 SP1 or earlier loses generic value settings when opened for reconfiguration in a later version of LabVIEW FPGA
671439 Using the Desktop Execution Node with an FPGA target VI that is within a .lvlib on the FPGA target throws Error 1055
673789 Errors thrown when executing the Desktop Execution Node can also be thrown when the FPGA VI is subsequently run in simulation mode without the Desktop Execution Node
674053 Using a VHDL file with the IP Integration Node that contains a generic and ends an entity declaration with "end entity" rather than "end [entity name]" will fail syntax check
677246 Using the IP Integration Node with a VHDL file that contains extender indentifiers results in the compilation failing with error [Synth 8-2139] illegal identifiers
725737 Digital Output timing outside of Single-Cycle Timed Loops has extra delay



ID Known Issue
648682

Return
The LabVIEW FPGA 2016 IP Builder will no longer function after upgrading the Xilinx Compilation Tool for Vivado 2015.4 that ships with the LabVIEW 2017 FPGA Module
Upgrading to the LabVIEW 2017 FPGA Xilinx Compilation Tool for Vivado 2015.4 from a previous installation of LabVIEW 2016 FPGA Module and LabVIEW 2016 FPGA Xilinx Compilation Tool for Vivado 2015.4 can cause IP Builder in 2016 to no longer function correctly. However, IP Builder in the LabVIEW 2017 FPGA Module will be functioning correctly.

Workaround: Repair or reinstall only the LabVIEW 2017 FPGA Xilinx Compilation Tool for Vivado 2015.4 installation.

Reported Version: 2017    Resolved Version: 2017 SP1    Added: 05/23/2017
629712

Return
A crash can occur when adding an FPGA Handshake into a cluster
Adding an FPGA Handshake item directly from the project into a cluster may cause a crash.

Workaround: Use a Handshake constant in the cluster to share a reference to the project item.

Reported Version: 2017    Resolved Version: 2018    Added: 05/23/2017
631368

Return
A crash can occur if evaluating FPGA refnums from a static FPGA reference in simulation
A crash can occur on a LabVIEW host VI if the Open FPGA VI Reference is not set to dynamic mode, and a probe or Not a Refnum? node is used in simulation.

Workaround: Use a dynamic FPGA reference or avoid those functions during simulation.

Reported Version: 2017    Resolved Version: 2018    Added: 05/23/2017
640863

Return
DMA channels are not available in the LabVIEW FPGA host interface if a DMA channel of type DBL is present
LabVIEW Communications supports DMA channels with a DBL datatype. If you have a bitfile compiled in this product that has a DMA channel of DBL type and try to use it in LabVIEW FPGA, you will not see any of the DMA channels available in that bitfile.

Workaround: Remove the DBL DMA channel from the original design and recompile the bitfile.

Reported Version: 2015 SP1    Resolved Version: 2018    Added: 05/23/2017
641409

Return
Library incompatibility during installations of the Xilinx Compilation Tool for Vivado on Linux
Some additional 32-bit libraries may be required during installations of the Xilinx Compilation Tool for Vivado on Red Hat Enterprise for Linux 7.0 and CentOS 7.0 (both 64-bit). These are only required for compiling designs that use Zynq-based FPGA targets. If this functionality is required, then be aware of a known compatibility issue between old versions of libselinux-policy and the latest libuuid as you upgrade.

Workaround: If you require these libraries for Zynq-based compilations, then it is strongly recommended to upgrade libselinux-policy before installing libuuid.i686 to avoid compatibility issues.

Reported Version: 2017    Resolved Version: N/A    Added: 05/23/2017
669283

Return
IP Integration Node saved in LabVIEW FPGA 2015 SP1 or earlier loses generic value settings when opened for reconfiguration in a later version of LabVIEW FPGA
If an IP Integration Node that has a top level VHDL file that contains a generic with a type that contains range information (i.e. integer range 2 to 16 ) is saved in LabVIEW FPGA 2015 SP1 or earlier and the IP Integration Node wizard is then opened in a later version of LabVIEW FPGA, the generic value settings will be reset to their default values

Workaround: N/A

Reported Version: 2015 SP1    Resolved Version: 2018    Added: 01/19/2018
671439

Return
Using the Desktop Execution Node with an FPGA target VI that is within a .lvlib on the FPGA target throws Error 1055
Pointing a Desktop Execution Node to a VI on an FPGA target that is contained within a .lvlib on the FPGA target throws Error 1055 after selecting 'OK' in the Select VI dialog box.

Workaround: Remove the FPGA target VI from the .lvlib.

Reported Version: 2017    Resolved Version: 2018    Added: 01/19/2018
673789

Return
Errors thrown when executing the Desktop Execution Node can also be thrown when the FPGA VI is subsequently run in simulation mode without the Desktop Execution Node
Errors thrown when running an FPGA VI with the Desktop Execution Node (DEN) can be thrown when running the same VI in simulation mode (without DEN) after the conditions leading to the error (i.e a broken VI) have been resolved.

Workaround: Close the FPGA VI before running the Desktop Execution Node.

Reported Version: 2017    Resolved Version: 2018    Added: 01/19/2018
674053

Return
Using a VHDL file with the IP Integration Node that contains a generic and ends an entity declaration with "end entity" rather than "end [entity name]" will fail syntax check
Using a VHDL file with the IP Integration Node that contains a generic and ends an entity declaration with "end entity" instead of "end [entity name]" will throw an error after clicking the Check Syntax button in the IP Integration Node wizard.

Workaround: Replace "end entity" with "end [entity name]" in the entity declaration.

Reported Version: 2017    Resolved Version: 2018    Added: 01/19/2018
677246

Return
Using the IP Integration Node with a VHDL file that contains extender indentifiers results in the compilation failing with error [Synth 8-2139] illegal identifiers
When compiling an FPGA VI that includes an IP Integration Node that is using a VHDL file with extended identifiers, the compilation fails with the error "[Synth 8-2139] illegal identifiers."

Workaround: Create a VHDL wrapper that does not use extended identifiers.

Reported Version: 2017    Resolved Version: 2018    Added: 01/19/2018
725737

Return
Digital Output timing outside of Single-Cycle Timed Loops has extra delay
In LabVIEW 2014 SP1 FPGA and earlier, using Digital Outputs outside of a Single-Cycle Timed Loop would result in the output taking only a single cycle of the FPGA Base Clock to execute. Currently this takes several additional clock cycles.

Workaround: Move Digital Outputs which have tight timing requirements into Single-Cycle Timed Loops.

Reported Version: 2015    Resolved Version: N/A    Added: 01/23/2019



Known Issues by Category

The following items are known issues in LabVIEW 2017 and 2017 SP1 FPGA Module sorted by Category.

Compatibility
640863 DMA channels are not available in the LabVIEW FPGA host interface if a DMA channel of type DBL is present
Installation and Activation
648682 The LabVIEW FPGA 2016 IP Builder will no longer function after upgrading the Xilinx Compilation Tool for Vivado 2015.4 that ships with the LabVIEW 2017 FPGA Module
641409 Library incompatibility during installations of the Xilinx Compilation Tool for Vivado on Linux
Miscellaneous
629712 A crash can occur when adding an FPGA Handshake into a cluster
631368 A crash can occur if evaluating FPGA refnums from a static FPGA reference in simulation
669283 IP Integration Node saved in LabVIEW FPGA 2015 SP1 or earlier loses generic value settings when opened for reconfiguration in a later version of LabVIEW FPGA
671439 Using the Desktop Execution Node with an FPGA target VI that is within a .lvlib on the FPGA target throws Error 1055
673789 Errors thrown when executing the Desktop Execution Node can also be thrown when the FPGA VI is subsequently run in simulation mode without the Desktop Execution Node
674053 Using a VHDL file with the IP Integration Node that contains a generic and ends an entity declaration with "end entity" rather than "end [entity name]" will fail syntax check
677246 Using the IP Integration Node with a VHDL file that contains extender indentifiers results in the compilation failing with error [Synth 8-2139] illegal identifiers
725737 Digital Output timing outside of Single-Cycle Timed Loops has extra delay



ID Known Issue
Compatibility
640863

Return
DMA channels are not available in the LabVIEW FPGA host interface if a DMA channel of type DBL is present
LabVIEW Communications supports DMA channels with a DBL datatype. If you have a bitfile compiled in this product that has a DMA channel of DBL type and try to use it in LabVIEW FPGA, you will not see any of the DMA channels available in that bitfile.

Workaround: Remove the DBL DMA channel from the original design and recompile the bitfile.

Reported Version: 2015 SP1    Resolved Version: 2018    Added: 05/23/2017
Installation and Activation
648682

Return
The LabVIEW FPGA 2016 IP Builder will no longer function after upgrading the Xilinx Compilation Tool for Vivado 2015.4 that ships with the LabVIEW 2017 FPGA Module
Upgrading to the LabVIEW 2017 FPGA Xilinx Compilation Tool for Vivado 2015.4 from a previous installation of LabVIEW 2016 FPGA Module and LabVIEW 2016 FPGA Xilinx Compilation Tool for Vivado 2015.4 can cause IP Builder in 2016 to no longer function correctly. However, IP Builder in the LabVIEW 2017 FPGA Module will be functioning correctly.

Workaround: Repair or reinstall only the LabVIEW 2017 FPGA Xilinx Compilation Tool for Vivado 2015.4 installation.

Reported Version: 2017    Resolved Version: 2017 SP1    Added: 05/23/2017
641409

Return
Library incompatibility during installations of the Xilinx Compilation Tool for Vivado on Linux
Some additional 32-bit libraries may be required during installations of the Xilinx Compilation Tool for Vivado on Red Hat Enterprise for Linux 7.0 and CentOS 7.0 (both 64-bit). These are only required for compiling designs that use Zynq-based FPGA targets. If this functionality is required, then be aware of a known compatibility issue between old versions of libselinux-policy and the latest libuuid as you upgrade.

Workaround: If you require these libraries for Zynq-based compilations, then it is strongly recommended to upgrade libselinux-policy before installing libuuid.i686 to avoid compatibility issues.

Reported Version: 2017    Resolved Version: N/A    Added: 05/23/2017
Miscellaneous
629712

Return
A crash can occur when adding an FPGA Handshake into a cluster
Adding an FPGA Handshake item directly from the project into a cluster may cause a crash.

Workaround: Use a Handshake constant in the cluster to share a reference to the project item.

Reported Version: 2017    Resolved Version: 2018    Added: 05/23/2017
631368

Return
A crash can occur if evaluating FPGA refnums from a static FPGA reference in simulation
A crash can occur on a LabVIEW host VI if the Open FPGA VI Reference is not set to dynamic mode, and a probe or Not a Refnum? node is used in simulation.

Workaround: Use a dynamic FPGA reference or avoid those functions during simulation.

Reported Version: 2017    Resolved Version: 2018    Added: 05/23/2017
669283

Return
IP Integration Node saved in LabVIEW FPGA 2015 SP1 or earlier loses generic value settings when opened for reconfiguration in a later version of LabVIEW FPGA
If an IP Integration Node that has a top level VHDL file that contains a generic with a type that contains range information (i.e. integer range 2 to 16 ) is saved in LabVIEW FPGA 2015 SP1 or earlier and the IP Integration Node wizard is then opened in a later version of LabVIEW FPGA, the generic value settings will be reset to their default values

Workaround: N/A

Reported Version: 2015 SP1    Resolved Version: 2018    Added: 01/19/2018
671439

Return
Using the Desktop Execution Node with an FPGA target VI that is within a .lvlib on the FPGA target throws Error 1055
Pointing a Desktop Execution Node to a VI on an FPGA target that is contained within a .lvlib on the FPGA target throws Error 1055 after selecting 'OK' in the Select VI dialog box.

Workaround: Remove the FPGA target VI from the .lvlib.

Reported Version: 2017    Resolved Version: 2018    Added: 01/19/2018
673789

Return
Errors thrown when executing the Desktop Execution Node can also be thrown when the FPGA VI is subsequently run in simulation mode without the Desktop Execution Node
Errors thrown when running an FPGA VI with the Desktop Execution Node (DEN) can be thrown when running the same VI in simulation mode (without DEN) after the conditions leading to the error (i.e a broken VI) have been resolved.

Workaround: Close the FPGA VI before running the Desktop Execution Node.

Reported Version: 2017    Resolved Version: 2018    Added: 01/19/2018
674053

Return
Using a VHDL file with the IP Integration Node that contains a generic and ends an entity declaration with "end entity" rather than "end [entity name]" will fail syntax check
Using a VHDL file with the IP Integration Node that contains a generic and ends an entity declaration with "end entity" instead of "end [entity name]" will throw an error after clicking the Check Syntax button in the IP Integration Node wizard.

Workaround: Replace "end entity" with "end [entity name]" in the entity declaration.

Reported Version: 2017    Resolved Version: 2018    Added: 01/19/2018
677246

Return
Using the IP Integration Node with a VHDL file that contains extender indentifiers results in the compilation failing with error [Synth 8-2139] illegal identifiers
When compiling an FPGA VI that includes an IP Integration Node that is using a VHDL file with extended identifiers, the compilation fails with the error "[Synth 8-2139] illegal identifiers."

Workaround: Create a VHDL wrapper that does not use extended identifiers.

Reported Version: 2017    Resolved Version: 2018    Added: 01/19/2018
725737

Return
Digital Output timing outside of Single-Cycle Timed Loops has extra delay
In LabVIEW 2014 SP1 FPGA and earlier, using Digital Outputs outside of a Single-Cycle Timed Loop would result in the output taking only a single cycle of the FPGA Base Clock to execute. Currently this takes several additional clock cycles.

Workaround: Move Digital Outputs which have tight timing requirements into Single-Cycle Timed Loops.

Reported Version: 2015    Resolved Version: N/A    Added: 01/23/2019

Document last updated on 1/23/2019

Glossary of Terms

 

  • Bug ID - When an issue is reported to NI, you may be given this ID or find it on ni.com.  You may also find IDs posted by NI on the discussion forums or in KnowledgeBase articles.
  • Legacy ID – An older issue ID that refers to the same issue.  You may instead find this issue ID in older known issues documents.
  • Description - A few sentences which describe the problem. The brief description given does not necessarily describe the problem in full detail.
  • Workaround - Possible ways to work around the problem.
  • Reported Version - The earliest version in which the issue was reported.
  • Resolved Version - Version in which the issue was resolved or was no longer applicable. "N/A" indicates that the issue has not been resolved.
  • Date Added - The date the issue was added to the document (not the reported date).