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This document contains the LabVIEW 8.0 FPGA Module known issues that were discovered before and since the release of the LabVIEW 8.0 FPGA Module. Not every issue known to NI will appear on this list; it is intended to only show the severe and more common issues that can be encountered.
Issues recorded after the LabVIEW FPGA Module version 8.0 released
Editting Host VI is Slow - Making edits to a host VI may be slow, especially when an FPGA VI has many front panel objects. Keep the FPGA VI open in memory to help speed up the edit process.
Front Panel Controls/Indicators missing from list in FPGA Read/Write node - Front Panel objects placed inside conditional disable structures on an FPGA VI can cause misalignment of the list of controls/indicators. Do not place front panel controls/indicators inside conditional disable structures.
"Unchanged" FPGA VIrequires recompile - Modifying items under the FPGA target in the project (like adding or removing I/O from the tree) changes the signature of the VI and causes a recompile to be required. This happens even if the functionality of the FPGA VIis not affected.
Issues with Importing FPGA Module 1.x Files
Save For Previous not supported - You cannot use the File»Save for Previous option with FPGA or FPGA Interface VIs and functions. In order to preserve your existing LabVIEW 7.x files National Instruments recommends you backup your files before importing them into LabVIEW 8.0.
Import utility changes the size of FPGA FIFOs that use block RAM - The import utility will cause FPGA FIFOs using block memory to change size. Right-click the FPGA FIFO in the Project Explorer window and select Properties from the shortcut menu to view the newly configured depth of the FIFO.
Imported Host VI broken - The host VI might import improperly into LabVIEW 8.0 if any of the following conditions apply:
You use constants for the HW Exec Ref parameter on the block diagram,
You use Call By Reference nodes that pass the HW Exec Ref parameter, or
You use strict type definitions of the HW Exec Ref parameter with property nodes to get or set their value.
Open the Host VI and manually replace all instances of the HW Exec Ref that are broken with the new HW Exec Ref coming from the Open FPGA VI Reference.
Imported FPGA VI broken - The FPGA VI might import improperly into LabVIEW 8.0 if you have multiple aliases pointing to the same resource or you have aliases with the same name that point to different resources. Edit the resources in the Project Explorer window.
Importing FPGA Module 1.0 VIs broken due to missing flag for Autopreallocate arrays and strings - An FPGA VI created with the FPGA module 1.0 might be broken after importing the VI into LabVIEW 8.0. Make sure that a checkmark appears in the Autopreallocate arrays and strings checkbox. You can find the checkbox by opening the FPGA VI, clicking File»VI Properties and selecting the Execution category.
Import utility replaces Abort method with Reset method - A host VI created with the FPGA module 1.x might have used the Abort method with an Invoke Method function or as part of the Close FPGA VI Reference function. The import utility replaces the Abort method with the Reset method.
The Abort method in the FPGA Module 1.x reset the FPGA VI to default values.
The Abort method In the FPGA Module 8.0 stops the FPGA VI but does not reset the values to their default values.
The Reset method in the FPGA Module 8.0 resets the FPGA VI to default values. By replacing the Abort method with the Reset method, the import utility preserves behavior of your program. No action on your part is necessary.
Mass Compile Tool prevents you from opening files in previous versions - You cannot use the File»Save for Previous option with FPGA or FPGA Interface VIs or functions. To continue using the VIs with the FPGA Module 1.x, do not use the mass compile tool on FPGA or FPGA Interface VIs from a previous version without first creating backup files.
Disable Legacy USB support on PXI Embedded Real-Time controllers - You must disable Legacy USB Support in the BIOS of PXI Embedded Real-Time Controllers when you use the FPGA Interface functions. Specific controllers affected are the PXI-817x controllers and any third-party systems that use the PhoenixBIOS. Failure to do so can result in the Open FPGA VI Reference function failing to download the FPGA VI without error. Subsequent reads using the Read/Write Control function may return values where all bits of the data type are set to 1. National Instruments also recommends disabling Legacy USB Support when you use the LabVIEW Real-Time Module to reduce jitter.
TCP must be installed - Most Windows installations have TCP installed. The LabVIEW FPGA Module communicates with the LabVIEW FPGA Compile Server through TCP. If TCP is not installed, LabVIEW returns the Error Contacting Server message when it attempts to contact the LabVIEW FPGA Compile Server. Refer to this Microsoft TechNet article for details on installing TCP/IP.
Do not edit FPGA VIs that are being compiled - You can click the Disconnect button in the Compiling VI for FPGA dialog box while an FPGA VI is being compiled to return to LabVIEW and edit VIs. However, do not edit any of the FPGA VIs that the LabVIEW FPGA Compile Server is compiling. If you want to edit the VIs being compiled, stop the current compilation process by clicking the Stop Compile button in the LabVIEW FPGA Compile Server window.
FPGA FIFO Reset Behavior - When you use an FPGA target emulator, FPGA FIFOs reset when the VI is stopped and started again. When you use an FPGA target with Interactive Front Panel Communication, FPGA FIFOs do not reset when the FPGA VI is stopped and started again. To reset the FIFO, right-click the FPGA Target in the Project Explorer window and select Reset from the shortcut menu. When you control an FPGA VI using Programmatic FPGA Interface Communication, use the Close FPGA VI Reference function with the Close and Reset shortcut menu option selected or the Invoke Method with the Reset method selected to reset FPGA FIFOs.
No FPGA download progress indication when running on an RT target - Pop-up windows are not supported in executables running on RT targets. Therefore, no pop-up window appears when an FPGA VI is programmatically downloaded by a host VI running on an RT target.
Windows XP Service Pack 2 displays security alert when you launch the LabVIEW FPGA Compile Server - If you have Windows XP Service Pack 2 installed, a security alert dialog box appears when you launch the LabVIEW FPGA Compile Server for the first time. If you select the Keep blocking this program option, the LabVIEW FPGA Compile Server cannot accept incoming connections from a remote computer. Select Unblock this program, despite the security risk, to configure your computer to launch the LabVIEW FPGA Compile Server without any changes in server functionality. Refer to KnowledgeBase 37AEQJVI: Security Alert Dialog Box Appears When Launching LabVIEW on Windows XP SP2 for more information about correcting this problem.
Slow installation/uninstallation progress - If you click the Modify button in the National Instruments Software dialog box after you install the LabVIEW FPGA Module, the installer can take up to 10 minutes to initialize.
Opening host VIs that include the FPGA Interface functions might take many minutes to open - Host VIs that contain the FPGA Interface functions might take a long time to open because the FPGA Interface functions need several support files to manage the interface with FPGA VIs. The FPGA Interface functions also verify the status of the FPGA VI when you open the host VI.