FlexRIO Support 16.0 Known Issues

Overview

This document contains the FlexRIO Support known issues that were discovered before and since the release of FlexRIO Support 16.0. Not every issue known to NI appears on this list; it is intended to show the most severe and common issues that can be encountered.

Each issue appears as a row in the table and includes the following fields:

  • Issue ID - The number in at the top of each of the cells in the first column. When you report an issue to NI, you may be given this ID, you can also find IDs posted by NI on the discussion forums or in Knowledge Base articles.  "N/A" indicates that there is no ID assigned to the issue.
  • Issue Title (in italics) - Describes the issue in one sentence or less.
  • Problem Description - A few sentences which describe the problem in further detail. The brief description given does not necessarily describe the problem in full detail, and it is expected that you may want more information on an issue. If you would like more information on an issue, contact NI and reference the ID number given in the document.
  • Workaround - Possible ways to work around the problem. The workarounds that appear in the document are not always tested by NI and are not guaranteed to resolve the issue. If a workaround refers you to the NI KnowledgeBase, visit www.ni.com/kb/ and enter the KnowledgeBase number in the search field to locate the specific document.
  • Reported Version - The earliest version of FlexRIO in which the issue was reported. If you discover the issue appears in an earlier version of FlexRIO than is reported in this field, report the discrepancy to NI to have the field updated.
  • Resolved Version - Version in which the issue was resolved or was no longer applicable. "N/A" indicates that the issue has not been resolved.
  • Date Added - The date the issue was added to the document (not the reported date).

Known Issues

603477 The DRAM FIFO instrument design library does not reset properly, and the status information is incorrect.
561398 FlexRIO example projects always search for CLIP in the Program Files (x86) folder, causing compilation to fail initially on 32-bit operating systems.
544097 The FlexRIO High-Throughput Streaming example calculates throughput incorrectly.
545599 The Controller for FlexRIO (NI-793XR) does not support debugging FPGA VIs using a third-party simulator.
526736 In the Streaming instrument design library, Wait For Stream.vi can return an incorrect value for the Samples Transferred output when an FPGA target is executed in Simulation mode.
489614 Synchronous CLIP signals are incorrectly allowed for use in asynchronous clock domains.
372645 PCI rebalancing occurs in certain hardware combinations or very large systems that include NI PXIe-796XR or NI PXIe-797XR FPGA modules, and may cause an operating system crash on boot.
597192 NI MAX and System Configuration API hang when using an unknown adapter module.
555601 DRAM on NI PXIe-797xR FPGA modules is inaccessible immediately after a download or reset of the FPGA.
596974 When synchronizing multiple NI 5752 or NI 5752B adapter modules there may be one sample of uncertainty.
583870 The NI 5752 adapter module inverts the analog input signals.
554346 The Aurora CLIP for the NI-793xR - MGT Aurora CLIP example may fail to initialize.
598087 In LabVIEW 2015, the NI-793xR - MGT Aurora CLIP example allocates an incorrect instruction address size on the FPGA.
611228 NI 6587 and NI 6589 examples return Error -52005: "The parameter received by the function is not valid." without changing anything within the example.
594173 A LabVIEW Real-Time system running the PharLAP OS can hang with 100% CPU usage during a reboot in some cases when using an NI PXIe-796XR FPGA module.



ID Known Issue
603477

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Issue: The DRAM FIFO instrument design library does not reset properly, and the status information is incorrect.

Public Details: The DRAM FIFO reset does not clear out all samples that reside within the boundary of the DRAM FIFO. Additionally, the status information provided by the DRAM FIFO Process VI incorrectly reports the number of samples within the boundary of the DRAM FIFO.

Public Workaround: Update to FlexRIO Support 16.1 or later. This fix applies only to LabVIEW 2016 support.

Reported Version: 16.0    Target Version for Fix: 16.1    Added: 12/16/2016/
561398

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Issue: FlexRIO example projects always search for CLIP in the Program Files (x86) folder, causing compilation to fail initially on 32-bit operating systems.

Public Details: The FlexRIO adapter module examples return a Missing CLIP implementation file error when compiling on a 32-bit OS. The LabVIEW project searches for the CLIP files for the adapter module in the C:\Program Files (x86)\National Instruments\ folder, which does not exist on a 32-bit OS.

Public Workaround: Open the IO Module Properties page and click the Reload button in the General category.

Reported Version: 16.0    Target Version for Fix: 16.1    Added: 12/16/2016/
544097

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Issue: The FlexRIO High-Throughput Streaming example calculates throughput incorrectly.

Public Details: The example does not accurately demonstrate how to stream at the full bandwidth on PXIe-797x FPGA modules.

Public Workaround: Either change the FIFO to write 8 I16s, or change the constants in the FPGA VI to 4 (Number of Elements Written).

Reported Version: 16.0    Target Version for Fix: 16.1    Added: 12/16/2016/
545599

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Issue: The Controller for FlexRIO (NI-793XR) does not support debugging FPGA VIs using a third-party simulator.

Public Details: The Controller for FlexRIO (NI-793XR) does not support the use of a third-party simulator to simulate and debug a LabVIEW FPGA VI.

Reported Version: 16.0    Target Version for Fix: 16.1    Added: 12/16/2016/
526736

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Issue: In the Streaming instrument design library, Wait For Stream.vi can return an incorrect value for the Samples Transferred output when an FPGA target is executed in Simulation mode.

Public Details: In the Streaming instrument design library, due to a race condition present only in Simulation mode, Wait For Stream.vi can return the second to last Samples Transferred value rather than the expected terminal value of a finite transfer.

Public Workaround: Do not use the Samples Transferred output from Wait For Stream.vi as the value for the Requested Elements input on a DMA FIFO when completing a finite transfer.

Reported Version: 16.0    Target Version for Fix: 16.1    Added: 12/16/2016/
489614

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Issue: Synchronous CLIP signals are incorrectly allowed for use in asynchronous clock domains.

Public Details: Certain FlexRIO adapter modules have CLIP signals that must be used in a clock domain provided by the CLIP. Accessing the IO node outside of that clock domain should cause a compilation error. Some adapter modules do not return a compilation error when the IO node is used in the wrong clock domain, resulting in glitched data.

Public Workaround: Recompile the FPGA VI with the IO node in the correct clock domain if using the NI 5751, NI 5752 or NI 5781 adapter modules.

Reported Version: 16.0    Target Version for Fix: 16.1    Added: 12/16/2016/
372645

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Issue: PCI rebalancing occurs in certain hardware combinations or very large systems that include NI PXIe-796XR or NI PXIe-797XR FPGA modules and may cause an operating system crash on boot.

Public Details: PCI rebalancing is the stopping and restarting of device drivers to rebalance a device's resources in memory. PCI rebalancing may take place on system boot for certain hardware combinations or very large systems. If the system contains an NI PXIe-796XR or NI PXIe-797XR FPGA module, this PCI rebalancing may cause an operating system crash.

Public Workaround: Update to FlexRIO Support 16.1 or later. Alternatively, to avoid rebalancing for an NI PXIe-796XR or NI PXIe-797XR FPGA module, ensure that the device driver is loaded after boot has completed. Right-click the device in Windows' Device Manager and select "Disable" before restarting or shutting down. After rebooting, select "Enable" in Windows' Device Manager to restore device functionality.

Reported Version: 16.0    Target Version for Fix: 16.1    Added: 12/16/2016/
597192

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Issue: NI MAX and System Configuration API hang when using an unknown adapter module.

Public Details: When an adapter module with an unknown IO Module ID is inserted into a FlexRIO FPGA Module, NI MAX and the System Configuration API in LabVIEW will hang or crash when querying properties of the FlexRIO FPGA Module.

Public Workaround: Update to FlexRIO 16.1 or later.

Reported Version: 16.0    Target Version for Fix: 16.1    Added: 12/16/2016/
555601

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Issue: DRAM on NI PXIe-797xR FPGA modules is inaccessible immediately after a download or reset of the FPGA.

Public Details: DRAM on NI PXIe-797xR FPGA modules is inaccessible immediately after a download or reset of the FPGA. A wait of at least 2.5 seconds must be added before before accessing the DRAM after an FPGA download or reset.

Public Workaround: After any reset or download of the FPGA, wait at least 2.5 seconds before accessing the DRAM.

Reported Version: 16.0    Target Version for Fix: 16.1    Added: 12/16/2016/
596974

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Issue: There may be one sample of uncertainty when synchronizing multiple NI 5752 or NI 5752B adapter modules.

Public Details: Due to a known issue in the constraints of the CLIPs for the NI 5752 and 5752B adapter modules there may be one sample of uncertainty when attempting to send the AdcTgcStart signal to the ADCs on the adapter modules. This may cause the gain sweep to start at different samples between adapter modules.

Reported Version: 16.0    Target Version for Fix: 16.1    Added: 12/16/2016/
583870

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Issue: The NI 5752 adapter module inverts the analog input signals.

Public Details: Each analog input signal acquired by the NI 5752 contain an incorrectly flipped signed bit which inverts the reported input signal.

Public Workaround: Invert the sign of the analog input signals coming from the CLIP.

Reported Version: 16.0    Target Version for Fix: 16.1    Added: 12/16/2016/
554346

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Issue: The Aurora CLIP for the NI-793xR - MGT Aurora CLIP example may fail to initialize.

Public Details: A design using the Aurora CLIP from the NI-793xR - MGT Aurora CLIP example project may fail to initialize after downloading a bitfile or resetting the FPGA.

Public Workaround: Use the status signals on the Aurora CLIP to determine if an error occurred and re-download the bitfile until the CLIP initializes without an error.

Reported Version: 16.0    Target Version for Fix: 16.1    Added: 12/16/2016/
598087

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Issue: In LabVIEW 2015, the NI-793xR - MGT Aurora CLIP example allocates an incorrect instruction address size on the FPGA.

Public Details: In LabVIEW 2015, compiling the NI-793xR - MGT Aurora CLIP example for the Controller for FlexRIO results in the following error:

"Error -250514 Possible reason(s): An AXI4-Lite address map element cannot fit in the specified address collection. Make sure that each address map elements' offset plus size does not exceed the address collection's total size."

Public Workaround: Update to FlexRIO 16.1 or later. Alternatively, open the block diagram of Create AXI4-Lite Resources.vi and increase the Address Space Size constant from 0x800 to 0x1200.

Reported Version: 16.0    Target Version for Fix: 16.1    Added: 12/16/2016/
611228

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Issue: NI 6587 and NI 6589 examples return Error -52005: "The parameter received by the function is not valid." without changing anything within the example.

Public Details: After installing FlexRIO 16.0, running NI 6587 and NI 6589 IO Module example programs in LabVIEW 2015 and LabVIEW 2016 results in Error -52005: "The parameter received by the function is not valid".

Public Workaround: In a new LabVIEW Project, create an NI 6587/6589 program from scratch using the broken examples as reference.

Reported Version: 16.0    Target Version for Fix: 16.1    Added: 12/16/2016/
594173

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Issue: A LabVIEW Real-Time system running the PharLAP OS can hang with 100% CPU usage during a reboot in some cases when using an NI PXIe-796XR FPGA module.

Public Details: In certain cases when using an NI PXIe-796XR FPGA module in a LabVIEW Real-Time system running the PharLAP OS, rebooting the computer can cause the system to hang when shutting down, requiring a hard shutdown in order to recover.

Public Workaround: Update to FlexRIO 16.1 or later. Alternatively, you can work around the issue by removing any Interrupt (IRQ) nodes from the FPGA VI running on the device, and ensuring that Target-to-Host FIFOs are only read when the number of elements requested are already available.

Reported Version: 16.0    Target Version for Fix: 16.1    Added: 12/16/2016/

Contacting NI

Contact NI regarding this document or issues in the document. If you contact NI in regards to a specific issue, reference the ID number given in the document. The ID number contains the current issue ID number as well as the legacy ID number (use the current ID number when contacting NI). You can contact us through any of the normal support channels including phone, email, or the discussion forums. Visit the NI Website to contact us. Also contact us if you find a workaround for an issue that is not listed in the document.

 

Related Resources

 

Glossary of Terms

 

  • Bug ID - When an issue is reported to NI, you may be given this ID or find it on ni.com.  You may also find IDs posted by NI on the discussion forums or in KnowledgeBase articles.
  • Legacy ID – An older issue ID that refers to the same issue.  You may instead find this issue ID in older known issues documents.
  • Description - A few sentences which describe the problem. The brief description given does not necessarily describe the problem in full detail.
  • Workaround - Possible ways to work around the problem.
  • Reported Version - The earliest version in which the issue was reported.
  • Resolved Version - Version in which the issue was resolved or was no longer applicable. "N/A" indicates that the issue has not been resolved.
  • Date Added - The date the issue was added to the document (not the reported date).