At the heart of the PXI-5922 oscilloscope is the next-generation flexible resolution converter, the Flex II ADC, which is built on a 27 GHz bipolar process. This section discusses the architecture of the Flex II ADC, which is an enhanced multibit delta-sigma converter.
Overview of Single-Bit Delta-Sigma ADCs
Figure 3 shows a block diagram of a simple single-bit delta-sigma ADC, which typically consists of a modulator and a digital signal processor (DSP).
Figure 3. Topology for Simple Single-Bit Delta-Sigma ADC
The single-bit modulator is comprised of a subtraction node, a loop filter, a 1-bit ADC, and a 1-bit DAC in a feedback loop. The ADC and DAC are oversampled at rates much higher than the desired sampling rate. The result of this oversampling is that the quantization noise is spread over a larger bandwidth, resulting in a lower noise floor as compared to other ADC architectures. This effect is illustrated in Figures 4 and 5.
Figure 4. In the FFT of a traditional (nonoversampled) ADC, quantization noise is distributed evenly up to Fs/2, where Fs is the sampling rate.
Figure 5. Effect of oversampling – the quantization noise is spread over a larger bandwidth up to kFs/2, where k is the oversampling factor. The result is a lower but spread-out noise floor.
The analog input signal is fed through a subtraction node to the analog loop filter, which has high gain at low frequencies and low gain at higher frequencies. This inherent characteristic makes it a lowpass filter. The quantization noise from the internal ADC is inversely proportional to the gain of the loop filter. As a result, the quantization noise gets highpass filtered in the feedback loop. This technique is referred to as ‘noise shaping’ and is illustrated in Figure 6.
Figure 6. Effect of noise shaping – the quantization noise is pushed into higher frequencies.
There is a change in the distribution of the quantization noise. The advantage of this kind of noise distribution is that most of the noise is concentrated in higher frequencies. This high-frequency noise can be easily eliminated in the digital domain by the application of a lowpass filter in the DSP. The signal is then decimated, which does not cause loss of information because the signal has been oversampled. Figure 7 illustrates the effect of the decimator.
Figure 7. Effects of the lowpass filter and decimator – elimination of the high-frequency noise and reduction of the sampling rate to Fs by decimation.
Flexible Resolution Flex II ADC - Fully Custom Analog ASIC
The Flex II ADC is an enhanced multibit delta-sigma ADC. The key enhancements over the simple single-bit delta-sigma ADC topology, which makes the outstanding performance possible, are as follows:
- Multibit ADC and DAC internal to the modulator
- Digital linearization and calibration
- Time-continuous loop filter
Figure 8 shows the block diagram of the Flex II ADC – an enhanced delta-sigma ADC.
Figure 8. Topology for the Enhanced Multibit Delta-Sigma ADC
Multibit ADC and DAC Internal to the Modulator
By eliminating most high-frequency noise, single-bit delta-sigma ADCs have high dynamic range. However, the major drawback of single-bit delta-sigma ADCs is that they operate at low frequencies and hence cannot be used in a variety of higher frequencies applications.
A solution to the frequency constraint problem of the single-bit delta-sigma ADC is the extension of the same basic principle to create a multibit delta-sigma ADC. Multibit delta-sigma ADCs, in theory, can achieve the same level of dynamic range as their single-bit counterparts, but at higher frequencies. However, multibit delta-sigma ADCs induce nonlinearities that have been a challenge to overcome until now.
The PXI-5922 is a 6-bit delta-sigma featuring a 6-bit ADC and DAC inside the modulator, each running at an oversampling rate of 120 MS/s. The induced nonlinearities caused by the multibit converter are reduced dramatically by the use of a patented linearization technique that results in the unprecedented dynamic range at higher frequencies.
Digital Linearization and Calibration
An elegant property of the feedback loop internal to the modulator is its ability to suppress errors. Unfortunately, this does not apply to errors in the feedback path of the loop. Hence conversion errors in the DAC are not attenuated and directly impact the quality of conversion from the modulator. The DAC degrades the total conversion quality in two ways:
- Analog noise in the output
The noise performance is controlled by design on the ASIC, but the required linearity performance is more difficult to handle.
Consider the simple 2-bit DAC shown in Figure 9. The DAC converter consists of three current generators (I1-I3) controlled by three switches (S1-S3). The resulting output current Iout depends on the number of switches being closed. In case of different current values, the DAC transfer function becomes nonlinear, as shown in Figure 9. For ideal operation of the converter, the three current generators must be equal. Further, switches S1-S3 must operate simultaneously.
Figure 9. A 2-bit DAC and its corresponding transfer function are nonlinear if the current values are not the same or if the switching is not simultaneous.
The optimal implementation of the DAC is on an integrated circuit, which guarantees the best possible matching of current values and switching times. Unfortunately, it is not possible even on a chip to obtain the performance required.
The traditional approach to enhance matching on a chip is to adjust the circuit, for example, by laser wafer trimming. But packaging, aging, and temperature variations will degrade the matching. Moreover, trimming also significantly adds to the production cost of the chip.
To circumvent these issues, the PXI-5922 uses a different approach. The unavoidable matching errors are compensated digitally by the DSP. With the patented National Instruments flexible resolution technology, current and timing errors are derived in circuit during self-calibration, which is more optimal than matching at the wafer level.
NI flexible resolution technology is used to derive the error parameters. A pure analog sine wave signal is applied to the converter during self-calibration and the errors are extracted from the digital response of the converter in a complex algorithm executed on the host PC.
Figure 10. FFT Plot of a Pure 3 kHz Sine Wave Applied to the 6-Bit Delta-Sigma ADC before Linearization
Figure 11. FFT Plot of a Pure 3 kHz Sine Wave Applied to the 6-Bit Delta-Sigma ADC after Linearization
Time-Continuous Loop Filter
The loop filter internal to the Flex II ADC is time continuous (TC) as opposed to the standard switched capacitor filter used in the conventional implementation. The TC implementation is difficult to integrate on chip because it requires precision passives. However, the TC implementation is not sensitive to aliasing, so internal noise sources in the modulator do not alias and accumulate in the passband. As a result, the converter has less noise and more resolution. Another important benefit is that it is much easier to integrate the converter into the noisy environment of a oscilloscope, because high-frequency switching noise is rejected by the alias-free operation of the converter.
These enhancements are not possible to integrate on a chip, and component vendors that traditionally have been driving converter technology are excluded from offering similar performance.
It’s More Than Just the High-Resolution ADC
In addition to having a high-performance ADC, it is important to have a front end that does not cause a performance bottleneck. The PXI-5922 features a world-class analog front end that takes full advantage of the high-performance Flex II ADC and frees the oscilloscope to provide unparalleled performance.
The input amplifier has software-selectable input impedances of 50 Ω and 1 MΩ. The 50 Ω input provides correct BNC cable termination and is useful in applications where frequency response is important. The 1 MΩ input mode is useful with sources that cannot drive 50 Ω without saturation or linearity degradation.
The oscilloscope contains a programmable-gain instrumentation amplifier (PGIA) with selectable input ranges of 1 and 5 V.
Synchronization and Memory Core
The PXI-5922 is built on the Synchronization and Memory Core1 (SMC) architecture, so you can tightly synchronize PXI-5922 modules with other SMC-based modular instruments using T-Clock2, an essential feature of SMC. This synchronization capability is critical when building mixed-signal test systems including signal generators, high-speed digital waveform generator/analyzers, and oscilloscopes. In addition, the SMC architecture provides up to 256 MB per channel of onboard memory on the PXI-5922 oscilloscope.