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I am using an NI FPGAdevice and want to use the on-board memory (DRAM) in my application When I configure DRAM to use, what is the Maximum Outstanding Requests for Data configuration option in the General ...

I have configured a user defined CLIP, when I route a internal clock it executes fine but when I route an external clock, it is not executing.

I would like to synchronize the FPGA clock of my R Series or FlexRIO PXI(e) board to the PXI(e) 10 MHz or 100 MHz backplane clock. Is this possible, and if so, how do I do this?

I want to use an FPGA Target on my hardware with the LabVIEWFPGA Module (64-Bit). Is this supported? My FPGA Target device driver installs LabVIEW 64-bit support, but when I try to add the module to a ...

I am trying to read a DMA FIFO on my host program but I receive Error -50400: Invoke Method:FIFO Read: Why is this happening?

I have a PXI FlexRIO FPGA module in a PXI chassis. I can see the PXI controller and chassis in NI MAX, but I can't see the card.

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