This document contains the LabVIEW FPGA Module 1.1 known issues that were discovered before and since the release of LabVIEW FPGA Module 1.1. Not every issue known to NI will appear on this list; it is intended to only show the severe and more common issues that can be encountered.
Here is a list of known issues relating to the LabVIEW FPGA Module Version 1.1 (requires LabVIEW 7.1).
NI PXI-7831R Environmental Specifications Changed - Environmental specifications for the NI PXI-7831R have changed. Refer to the NI 7831R User Manual, available at ni.com/manuals, for the updated operating temperature limits.
Disable Legacy USB Support on PXI Embedded Real-Time Controllers - You must disable Legacy USB Support in the BIOS of PXI Embedded Real-Time Controllers when you use the FPGA Interface functions. Specific controllers affected are the PXI-817x controllers and any other third-party systems that use the PhoenixBIOS. Failure to do so can result in the Open FPGA VI Reference function failing to download the FPGA VI without returning an error. Subsequent reads using the Read/Write function will return values where all bits of the data type are set to 1 without an error. National Instruments also recommends disabling Legacy USB Support when using the LabVIEW Real-Time Module to reduce jitter.
Save For Previous Not Supported - You cannot use the File»Save for Previous option with FPGA or FPGA Interface VIs and functions. Back up all of your existing LabVIEW 7.0 files before opening them with LabVIEW 7.1.
TCP Must Be Installed - Most Windows installations have TCP installed. The LabVIEW FPGA Module communicates with the LabVIEW FPGA Compile Server through TCP. If TCP is not installed, LabVIEW returns the Error Contacting Server message when it attempts to contact the LabVIEW FPGA Compile Server.
Stop VIs Before Switching Execution Targets - If you do not stop VIs before switching execution targets, you might obtain unexpected results.
FPGA Interface: Simultaneous Reads/Write to Arrays or Clusters Can Return Bad Data - You can use the Read/Write Control function on the FPGA Interface palette to read or write to arrays or clusters on the front panel of the FPGA VI. If you read or write to two locations in the host VI at the same time, LabVIEW might return bad data. Make sure that reading or writing to an array or cluster does not occur in parallel with any other reading or writing to the same array or cluster.
Do Not Edit FPGA VIs That Are Being Compiled - You can click the Disconnect button in the Compiling VI for FPGA dialog box while an FPGA VI is being compiled to return to LabVIEW and edit VIs. However, you must not edit any of the FPGA VIs that the LabVIEW FPGA Compile Server is compiling. If you want to edit the VIs being compiled, stop the current compilation process by clicking the Stop Compile button in the LabVIEW FPGA Compile Server window.
Embedded Project Manager Takes a Long Time to Launch - When the Embedded Project Manager window launches, it searches for FPGA devices. If you have remote systems enabled for remote finding in Measurement & Automation Explorer (MAX) and those systems are not accessible, the Embedded Project Manager window launches slowly due to connection timeouts. Refer to the LabVIEW FPGA Module Release Notes for more information about enabling and disabling remote finding in MAX.
FPGA FIFO Reset Behavior - When you target an FPGA device emulator, FPGA FIFOs reset when the VI is stopped and then started again. When you target an FPGA device and use Interactive Front Panel Communication, FPGA FIFOs do not reset when the FPGA VI is stopped and then started again. To reset the FIFO, select Operate»Download Application. When you control an FPGA VI using Programmatic FPGA Interface Communication, use the Close FPGA VI Reference function with the Close and Abort shortcut menu options selected to reset FPGA FIFOs.
Consider Using the VISA Resource Name Input on the Open FPGA VI Reference Function for Systems with Multiple FPGA Devices - By default, the Open FPGA VI Reference function uses relative addressing. However, relative addresses can change. For example, if you have one FPGA device installed in your development computer, its relative address is 0. If you then enable remote finding for a remote system with additional FPGA devices, the address of the FPGA device in your local development computer changes. To create a program with static references, use the VISA Resource Name input by right-clicking the Open FPGA VI Reference function and selecting External VISA Input from the shortcut menu. The Open FPGA VI Reference function now has an additional input to which you can wire an FPGA device VISA resource name. Refer to the LabVIEW Help, available by selecting Help»VI, Function, & How-To Help in LabVIEW, for more information about the Open FPGA VI Reference function and relative addressing.
Using the Application Builder - The Open FPGA VI Reference function checks that the FPGA Interface is up to date and that the bitfile is up to date. You will receive an error if either of these checks fails. LabVIEW disables these checks when you build the Open FPGA VI Reference function into an executable. Before you build an application using the Application Builder, run the host VI to verify that the FPGA Interface functions interact properly with the FPGA VI with no errors.
An asterisk "*" appears in the VI Title Bar of an FPGA VI After Switching Targets - After you create and compile an FPGA VI and switch execution targets to LabVIEW for Windows or an RT target, the VI name might have an asterisk "*" after it in the VI title bar. The asterisk indicates the VI has changed. When you target LabVIEW for Windows or an RT target, the VI is compiled for LabVIEW for Windows or an RT target as well as for the FPGA device. You can save the FPGA VI without having to recompile it for the FPGA device again.
Unconnected Output on FPGA Device I/O Functions Causes Compile Errors - Delete the unused terminals or create indicators for the unused terminals to avoid these compilation errors.
Error 1073 When Building Applications - When you build applications from FPGA VIs or host VIs using the Application Builder, make sure the Disconnect type definitions and remove unused polymorphic VI instances checkbox contains a checkmark. If you receive Error 1073 while building an application, the error might tell you to uncheck this option. Instead, make sure that the Just-In-Time Advice dialog box is closed.
Slow Installer Progress - If you click the Modify button in the National Instruments Software dialog box, available in the Add or Remove Programs utility, after you install the LabVIEW FPGA Module, the installer can take up to 10 minutes to initialize.
Do Not Use Tab Controls in an FPGA VI - If you place controls or indicators on a tab control they can behave incorrectly. If you must use a tab control, you need to test every control and indicator on the tab control and make sure all operate correctly. If controls are responding correctly, they will continue to respond correctly. You cannot use nested tab controls in FPGA VIs. Do not group controls or indicators on a tab control in an FPGA VI. Grouping controls and indicators on a tab control causes incorrect behavior.
No FPGA Download Progress Indication When Running on an RT Target - Pop-up windows are not supported in executables running on RT targets. Therefore, no pop-up window appears to indicate when an FPGA VI is programmatically downloaded by a host VI running on an RT target.
Fitting Large FPGA VIs - The LabVIEW FPGA Module, version 1.0, optimized compiles for space utilization on the FPGA. By default, the LabVIEW FPGA Module, version 1.1, optimizes for speed. Refer to the Knowledge Base Document ID 37BERJM9, available at ni.com/support, if you want to try optimizing for space utilization on the FPGA.
Windows XP Service Pack 2 Displays Security Alert When You Launch the LabVIEW FPGA Compile Server - If you have Windows XP Service Pack 2 installed, a Security Alert dialog box appears when you launch the LabVIEW FPGA Compile Server for the first time. If you select the Keep blocking this program option, the LabVIEW FPGA Compile Server cannot accept incoming connections from a remote computer. Select the Unblock this program, despite the security risk option to configure your computer to launch the LabVIEW FPGA Compile Server without any changes in server functionality. Refer to the KnowledgeBase for more information about correcting this problem.