LabVIEW Communications System Design Suite 2.0 Known Issues

Aperçu

This document contains the LabVIEW Communications System Design Suite 2.0 known issues that were discovered before and since the release of LabVIEW Communications System Design Suite 2.0. Not every issue known to NI will appear on this list; it is intended to only show the severe and more common issues that can be encountered.

Known Issues by Date

The following items are known issues in LabVIEW Communications System Design Suite 2.0 sorted by Date.

563511 Some chassis slots appear blank in SystemDesigner with no description why
571822 A crash may occur when trying to compile a bitfile from a previous version's project if the FPGA target was copied
572029 Right-Click and Context Palette nodes get cropped when text size to 125%
572838 Reported Compile Duration may be incorrect after reconnecting to compilation
572970 Previous version VIs will not mutate correctly if the VI is placed on SystemDesigner without any targets
576267 Under certain conditions, adding a GCDL document to the VI under a PC target will display the icon incorrectly
577273 Using Save All after modifying both a VI and a Typedef may cause the VI to appear to require an additional save
578591 "Conflicting Items Exist" dialog pops up in error during project reload if the running VI was added to the project before the project was saved
584478 Comparison mode setting is not preserved when converting LabVIEW comparison nodes with waveforms as inputs
584767 Some UI elements in the LabVIEW Communications environment may not display correctly using custom DPI settings
587454 Including a large number of files in the project at once can cause LabVIEW Communications to hang
587522 Changing the build spec from "Bitfile" to "None" during compilation will cause the compilation to fail
589526 Large local FIFOs may cause unsuccessful compilations
590787 DRAM Access Time should not be set to a value of 1
591575 MRD QR Decomposition example may display mismatched data values
592178 Editing subVI terminals while that subVI is set to List View in a calling VI can cause the project to crash
594363 Charts will not display a cluster of Fixed Point data types
595935 Profiling fixed-point data for a CDB array may cause the application to hang



ID Known Issue
563511

Return
Some chassis slots appear blank in SystemDesigner with no description why
Chassis such as the PXIe-1062Q include slots that may not be supported in LabVIEW Communications. These slots still show on SystemDesigner but there is no ability to interact with them and no indication why.

Workaround: Blank chassis slots indicate an unsupported slot in LabVIEW Communications.

Reported Version: 2.0    Resolved Version: N/A    Added: 08/01/2016
571822

Return
A crash may occur when trying to compile a bitfile from a previous version's project if the FPGA target was copied
Trying to compile a VI under an FPGA target that was copied and pasted on SystemDesigner in a previous version may cause an unexpected crash.

Workaround: Rebuild the targets on SystemDesigner from new rather than copying and pasting.

Reported Version: 2.0    Resolved Version: N/A    Added: 08/01/2016
572029

Return
Right-Click and Context Palette nodes get cropped when text size to 125%
If the user has their system to show text at 125%, the nodes in the Right-click and Context Palettes may not display correctly.

Workaround: Adjust operating system settings to display text at a setting less than 125%.

Reported Version: 2.0    Resolved Version: N/A    Added: 08/01/2016
572838

Return
Reported Compile Duration may be incorrect after reconnecting to compilation
If a disconnection and re-connection occurs during an FPGA compilation, then Total Duration and Compile Time information may be displayed incorrectly on the bitfile document.

Workaround: This issue only affects Total Duration and Compile Time displayed on the bitfile document. The elapsed time of each compile step is still correct and this issue does not affect functionality of the actual compilation process.

Reported Version: 1.1    Resolved Version: N/A    Added: 08/01/2016
572970

Return
Previous version VIs will not mutate correctly if the VI is placed on SystemDesigner without any targets
A VI placed on SystemDesigner without any targets in LabVIEW Communications 1.1, and earlier, will not mutate correctly when importing into newer versions.

Workaround: Place the VI within the correct target context prior to upgrading the project.

Reported Version: 2.0    Resolved Version: N/A    Added: 08/01/2016
576267

Return
Under certain conditions, adding a GCDL document to the VI under a PC target will display the icon incorrectly
When a GCDL document exists under two FPGA targets and is added to a VI under a PC target, the icon will display incorrectly.

Workaround: Ensure that the GCDL is within a VI for a valid target.

Reported Version: 2.0    Resolved Version: N/A    Added: 08/01/2016
577273

Return
Using Save All after modifying both a VI and a Typedef may cause the VI to appear to require an additional save
Since Typedefs update usages on saves, there can be a race condition where the VI is saved before the Typdef. This shows that the VI requires an additional save despite being saved already.

Workaround: The changes will be saved so there is no loss of data. However, saving files individually, or making changes to Typedefs and related VIs separately, can help avoid the need for additional saves.

Reported Version: 2.0    Resolved Version: N/A    Added: 08/01/2016
578591

Return
"Conflicting Items Exist" dialog pops up in error during project reload if the running VI was added to the project before the project was saved
When loading a project that contains a Real-Time target, there is an attempt to connect ,and attach, to any already running VIs on the target. When the VI in the project matches the VI running on the target, it should seamlessly attach and the VI's panel state should reflect the current state of the running VI on the target. However, if the VI was created, or added, to the project before the project had ever been saved, the attach always fails and a conflict dialog is displayed.

Workaround: Always save the project before adding any VIs.

Reported Version: 1.0    Resolved Version: N/A    Added: 08/01/2016
584478

Return
Comparison mode setting is not preserved when converting LabVIEW comparison nodes with waveforms as inputs
When converting VIs which compare waveforms using the following nodes: IsGreater, IsGreaterOrEqual, IsLess and IsLessOrEqual, the Comparison Mode setting is not preserved. It will be set to the default value of "Compare Elements". If the original VI has "Compare Aggregates" set, the converted VI will have a broken wire output from the comparison node. This is because the data type of the output is not the same for the two modes.

Workaround: Visit each comparison node with a broken wire and set the "Comparison Mode" to "Compare Aggregates".

Reported Version: 2.0    Resolved Version: N/A    Added: 08/01/2016
584767

Return
Some UI elements in the LabVIEW Communications environment may not display correctly using custom DPI settings
Some UI elements may display incompletely if using a custom Windows DPI setting of 125%, or similar.

Workaround: Use default DPI settings.

Reported Version: 2.0    Resolved Version: N/A    Added: 08/01/2016
587454

Return
Including a large number of files in the project at once can cause LabVIEW Communications to hang
Adding a large number of files to the project from the Navigation Pane can cause the application to hang or become unresponsive for a time.

Workaround: Minimize the number of files added at the same time. Add smaller groups of files more often rather than all at once.

Reported Version: 2.0    Resolved Version: N/A    Added: 08/01/2016
587522

Return
Changing the build spec from "Bitfile" to "None" during compilation will cause the compilation to fail
Changing the build spec from "Bitfile" to "None" during compilation will cause the compilation to fail.

Workaround: Do not modify the build spec during compilation.

Reported Version: 2.0    Resolved Version: N/A    Added: 08/01/2016
589526

Return
Large local FIFOs may cause unsuccessful compilations
Creating local FIFOs near the maximum allowable sizes may cause compilations to fail with the message "There is a problem with one or more of the VIs associated with the compile".

Workaround: Reduce the total size of the FIFO .

Reported Version: 2.0    Resolved Version: N/A    Added: 08/01/2016
590787

Return
DRAM Access Time should not be set to a value of 1
DRAM Access Time should be set to any positive number other than 1 in order to work properly.

Workaround: DRAM Access Time should be set to any positive number other than 1 in order to work properly.

Reported Version: 2.0    Resolved Version: N/A    Added: 08/01/2016
591575

Return
MRD QR Decomposition example may display mismatched data values
When running the MRD QR Decomposition example, and viewing the data comparison from FPGA to host, there may be inconsistent values displayed. This is due to data coercion.

Workaround: Change the Q and R array indicators to the Double data type to get rid of the coercions.

Reported Version: 2.0    Resolved Version: N/A    Added: 08/01/2016
592178

Return
Editing subVI terminals while that subVI is set to List View in a calling VI can cause the project to crash
A subVI called from another VI can have its Visual Style set to either Icon or List at the callsite. When set to List, calling VIs may not be able to properly propagate terminal edits made to that subVI. This can result in subsequent project crashes when trying to open the calling VI.

Workaround: Switch subVI calls to Icon view instead of List view when rearranging terminals.

Reported Version: 2.0    Resolved Version: N/A    Added: 08/01/2016
594363

Return
Charts will not display a cluster of Fixed Point data types
Charts will not correctly display data for clusters containing one, or more, Fixed Point (FXP) data types. No error, or warning, is displayed but a subsequent crash may occur after VI execution. Charts will display correctly for Fixed Point data types not bundled into a cluster.

Workaround: Use other data types in place of Fixed Points if bundling clusters of Chart data.

Reported Version: 2.0    Resolved Version: N/A    Added: 08/01/2016
595935

Return
Profiling fixed-point data for a CDB array may cause the application to hang
If a design includes an array of complex double floating-point data types, and the "Profile Fixed Point Data" option is enabled for the VI, then running the VI in simulation may cause the application to hang and become unresponsive.

Workaround: Split CDB arrays into real and imaginary arrays for fixed-point profiling.

Reported Version: 2.0    Resolved Version: N/A    Added: 08/01/2016



Known Issues by Category

The following items are known issues in LabVIEW Communications System Design Suite 2.0 sorted by Category.

Example Programs
591575 MRD QR Decomposition example may display mismatched data values
LabVIEW Project
576267 Under certain conditions, adding a GCDL document to the VI under a PC target will display the icon incorrectly
577273 Using Save All after modifying both a VI and a Typedef may cause the VI to appear to require an additional save
578591 "Conflicting Items Exist" dialog pops up in error during project reload if the running VI was added to the project before the project was saved
587454 Including a large number of files in the project at once can cause LabVIEW Communications to hang
Miscellaneous
563511 Some chassis slots appear blank in SystemDesigner with no description why
572029 Right-Click and Context Palette nodes get cropped when text size to 125%
572838 Reported Compile Duration may be incorrect after reconnecting to compilation
584767 Some UI elements in the LabVIEW Communications environment may not display correctly using custom DPI settings
587522 Changing the build spec from "Bitfile" to "None" during compilation will cause the compilation to fail
589526 Large local FIFOs may cause unsuccessful compilations
590787 DRAM Access Time should not be set to a value of 1
592178 Editing subVI terminals while that subVI is set to List View in a calling VI can cause the project to crash
594363 Charts will not display a cluster of Fixed Point data types
595935 Profiling fixed-point data for a CDB array may cause the application to hang
Upgrade - Migration
571822 A crash may occur when trying to compile a bitfile from a previous version's project if the FPGA target was copied
572970 Previous version VIs will not mutate correctly if the VI is placed on SystemDesigner without any targets
584478 Comparison mode setting is not preserved when converting LabVIEW comparison nodes with waveforms as inputs



ID Known Issue
Example Programs
591575

Return
MRD QR Decomposition example may display mismatched data values
When running the MRD QR Decomposition example, and viewing the data comparison from FPGA to host, there may be inconsistent values displayed. This is due to data coercion.

Workaround: Change the Q and R array indicators to the Double data type to get rid of the coercions.

Reported Version: 2.0    Resolved Version: N/A    Added: 08/01/2016
LabVIEW Project
576267

Return
Under certain conditions, adding a GCDL document to the VI under a PC target will display the icon incorrectly
When a GCDL document exists under two FPGA targets and is added to a VI under a PC target, the icon will display incorrectly.

Workaround: Ensure that the GCDL is within a VI for a valid target.

Reported Version: 2.0    Resolved Version: N/A    Added: 08/01/2016
577273

Return
Using Save All after modifying both a VI and a Typedef may cause the VI to appear to require an additional save
Since Typedefs update usages on saves, there can be a race condition where the VI is saved before the Typdef. This shows that the VI requires an additional save despite being saved already.

Workaround: The changes will be saved so there is no loss of data. However, saving files individually, or making changes to Typedefs and related VIs separately, can help avoid the need for additional saves.

Reported Version: 2.0    Resolved Version: N/A    Added: 08/01/2016
578591

Return
"Conflicting Items Exist" dialog pops up in error during project reload if the running VI was added to the project before the project was saved
When loading a project that contains a Real-Time target, there is an attempt to connect ,and attach, to any already running VIs on the target. When the VI in the project matches the VI running on the target, it should seamlessly attach and the VI's panel state should reflect the current state of the running VI on the target. However, if the VI was created, or added, to the project before the project had ever been saved, the attach always fails and a conflict dialog is displayed.

Workaround: Always save the project before adding any VIs.

Reported Version: 1.0    Resolved Version: N/A    Added: 08/01/2016
587454

Return
Including a large number of files in the project at once can cause LabVIEW Communications to hang
Adding a large number of files to the project from the Navigation Pane can cause the application to hang or become unresponsive for a time.

Workaround: Minimize the number of files added at the same time. Add smaller groups of files more often rather than all at once.

Reported Version: 2.0    Resolved Version: N/A    Added: 08/01/2016
Miscellaneous
563511

Return
Some chassis slots appear blank in SystemDesigner with no description why
Chassis such as the PXIe-1062Q include slots that may not be supported in LabVIEW Communications. These slots still show on SystemDesigner but there is no ability to interact with them and no indication why.

Workaround: Blank chassis slots indicate an unsupported slot in LabVIEW Communications.

Reported Version: 2.0    Resolved Version: N/A    Added: 08/01/2016
572029

Return
Right-Click and Context Palette nodes get cropped when text size to 125%
If the user has their system to show text at 125%, the nodes in the Right-click and Context Palettes may not display correctly.

Workaround: Adjust operating system settings to display text at a setting less than 125%.

Reported Version: 2.0    Resolved Version: N/A    Added: 08/01/2016
572838

Return
Reported Compile Duration may be incorrect after reconnecting to compilation
If a disconnection and re-connection occurs during an FPGA compilation, then Total Duration and Compile Time information may be displayed incorrectly on the bitfile document.

Workaround: This issue only affects Total Duration and Compile Time displayed on the bitfile document. The elapsed time of each compile step is still correct and this issue does not affect functionality of the actual compilation process.

Reported Version: 1.1    Resolved Version: N/A    Added: 08/01/2016
584767

Return
Some UI elements in the LabVIEW Communications environment may not display correctly using custom DPI settings
Some UI elements may display incompletely if using a custom Windows DPI setting of 125%, or similar.

Workaround: Use default DPI settings.

Reported Version: 2.0    Resolved Version: N/A    Added: 08/01/2016
587522

Return
Changing the build spec from "Bitfile" to "None" during compilation will cause the compilation to fail
Changing the build spec from "Bitfile" to "None" during compilation will cause the compilation to fail.

Workaround: Do not modify the build spec during compilation.

Reported Version: 2.0    Resolved Version: N/A    Added: 08/01/2016
589526

Return
Large local FIFOs may cause unsuccessful compilations
Creating local FIFOs near the maximum allowable sizes may cause compilations to fail with the message "There is a problem with one or more of the VIs associated with the compile".

Workaround: Reduce the total size of the FIFO .

Reported Version: 2.0    Resolved Version: N/A    Added: 08/01/2016
590787

Return
DRAM Access Time should not be set to a value of 1
DRAM Access Time should be set to any positive number other than 1 in order to work properly.

Workaround: DRAM Access Time should be set to any positive number other than 1 in order to work properly.

Reported Version: 2.0    Resolved Version: N/A    Added: 08/01/2016
592178

Return
Editing subVI terminals while that subVI is set to List View in a calling VI can cause the project to crash
A subVI called from another VI can have its Visual Style set to either Icon or List at the callsite. When set to List, calling VIs may not be able to properly propagate terminal edits made to that subVI. This can result in subsequent project crashes when trying to open the calling VI.

Workaround: Switch subVI calls to Icon view instead of List view when rearranging terminals.

Reported Version: 2.0    Resolved Version: N/A    Added: 08/01/2016
594363

Return
Charts will not display a cluster of Fixed Point data types
Charts will not correctly display data for clusters containing one, or more, Fixed Point (FXP) data types. No error, or warning, is displayed but a subsequent crash may occur after VI execution. Charts will display correctly for Fixed Point data types not bundled into a cluster.

Workaround: Use other data types in place of Fixed Points if bundling clusters of Chart data.

Reported Version: 2.0    Resolved Version: N/A    Added: 08/01/2016
595935

Return
Profiling fixed-point data for a CDB array may cause the application to hang
If a design includes an array of complex double floating-point data types, and the "Profile Fixed Point Data" option is enabled for the VI, then running the VI in simulation may cause the application to hang and become unresponsive.

Workaround: Split CDB arrays into real and imaginary arrays for fixed-point profiling.

Reported Version: 2.0    Resolved Version: N/A    Added: 08/01/2016
Upgrade - Migration
571822

Return
A crash may occur when trying to compile a bitfile from a previous version's project if the FPGA target was copied
Trying to compile a VI under an FPGA target that was copied and pasted on SystemDesigner in a previous version may cause an unexpected crash.

Workaround: Rebuild the targets on SystemDesigner from new rather than copying and pasting.

Reported Version: 2.0    Resolved Version: N/A    Added: 08/01/2016
572970

Return
Previous version VIs will not mutate correctly if the VI is placed on SystemDesigner without any targets
A VI placed on SystemDesigner without any targets in LabVIEW Communications 1.1, and earlier, will not mutate correctly when importing into newer versions.

Workaround: Place the VI within the correct target context prior to upgrading the project.

Reported Version: 2.0    Resolved Version: N/A    Added: 08/01/2016
584478

Return
Comparison mode setting is not preserved when converting LabVIEW comparison nodes with waveforms as inputs
When converting VIs which compare waveforms using the following nodes: IsGreater, IsGreaterOrEqual, IsLess and IsLessOrEqual, the Comparison Mode setting is not preserved. It will be set to the default value of "Compare Elements". If the original VI has "Compare Aggregates" set, the converted VI will have a broken wire output from the comparison node. This is because the data type of the output is not the same for the two modes.

Workaround: Visit each comparison node with a broken wire and set the "Comparison Mode" to "Compare Aggregates".

Reported Version: 2.0    Resolved Version: N/A    Added: 08/01/2016

Glossary of Terms

 

  • Bug ID - When an issue is reported to NI, you may be given this ID or find it on ni.com.  You may also find IDs posted by NI on the discussion forums or in KnowledgeBase articles.
  • Legacy ID – An older issue ID that refers to the same issue.  You may instead find this issue ID in older known issues documents.
  • Description - A few sentences which describe the problem. The brief description given does not necessarily describe the problem in full detail.
  • Workaround - Possible ways to work around the problem.
  • Reported Version - The earliest version in which the issue was reported.
  • Resolved Version - Version in which the issue was resolved or was no longer applicable. "N/A" indicates that the issue has not been resolved.
  • Date Added - The date the issue was added to the document (not the reported date).