The following sections detail two methods for determining the settling time of your DAQ board – one with DC signals and one with AC signals.
DC Signal Settling-Time Test
Figure 5 shows the DC signal test, in which two DC signals are connected to the DAQ board. To run the test, connect a ± signal to channels 1 and 2, respectively. The input signals should be close to but not above the DAQ board full-scale input range when a high gain is applied. For example, a ±0.048 V input with a gain of 100 results in a 4.8 V signal, which is 0.2 V less than the full-scale value of the board. When running this test, it is important that you do not input a signal greater than or equal to the full-scale value because this can saturate the amplifier and result in a longer settling time. Next, complete at least a 100-point single-channel timed data acquisition for each channel and average the results to obtain a positive and a negative reference voltage. In Figure 5, these reference voltages are represented by the lines labeled VREF and -VREF.
After acquiring the reference values individually, acquire 100 points at the maximum sampling rate for the two channels, alternating the sampling between the channels; this is also called scanning the channels. Figure 5 shows these points as dots near the reference voltage lines.
Again, average the data; you will use this average to calculate the settling-time error at the maximum sampling rate. In Figure 5, the average of the positive data is 0.04 V; the average of the negative data is –0.048 V.
To calculate the error, compute the maximum deviation between the reference voltages and the positive and negative averages of the scanned data; in other words, subtract the averaged scanned data from the positive and negative reference voltages and use the maximum of the absolute values. This deviation is the amount of settling-time error in voltage at the maximum sampling rate. In the example in Figure 5, the positive and negative deviations are 0.01 V and –0.002 V respectively, which results in a maximum settling-time error of 0.01 V.
Figure 5. DC Signal Settling-Time Test
Repeat this process at different sampling rates and gains until the board settles to the specified accuracy. To plot the error in least-significant bits (LSBs) versus time, divide the absolute value of the maximum deviation by the voltage equal to 1 LSB for the gain you applied. For example, in Figure 5,
at a gain of 100. Therefore, the error of 0.01 V in Figure 5 equals 409.8 LSBs. Invert the sampling rate to calculate the settling time with that particular amount of error. At a sampling rate of 100 kS/s, for example, the settling time is 10µs. After the plot is complete, compare the plot to the specified board accuracy to see how long your board takes to settle to the specified accuracy.
AC Signal Settling-Time Test
Figure 6 shows the AC signal test. In Figure 6, a full-scale low-frequency AC signal is connected to channel 1, and channel 2 is connected to ground. By alternating the sampling between both channels (scanning) at the maximum sampling rate, as shown in the top graph in Figure 6, and performing a fast Fourier transform (FFT) on the data from channel 2, as shown in the bottom graph, you can see if the amplifier correctly settled.
If any large spikes appear in the FFT plot at the frequency of the channel 1 input signal, as in Figure 6, the amplifier did not settle completely. The magnitude of the spike is the amount of voltage error; the corresponding settling time is the inverse of the sampling rate. Notice that using an input signal that is too high in frequency could cause crosstalk, which would appear the same as a settling-time error in the channel 2 spectrum.
Note: Crosstalk is an expected natural phenomenon caused by the close proximity of signals and capacitance, which results in unwanted coupling of the signals. All DAQ boards have a measure of crosstalk.
Figure 6. AC Signal Settling-Time Test
Repeat this process with different sampling rates and gains to see how quickly the amplifier settles and with what amount of error. When you have minimized the magnitude of the spike in the FFT plot, the amplifier has settled correctly. You can use this process to determine the sampling rate and gain at which you can acquire data accurately with your DAQ board.