Returning to the example of design and test convergence within RF, communication design introduces a few unique complexities to the general trend of convergence. Most significantly, to test an RF receiver you must create a transmitter, and to test a transmitter you must create a receiver. Oftentimes, the signal and measurement characteristics of these testers must surpass that of the design itself. Additionally, the rate of change of RF communication approaches and standards is extremely fast, requiring flexibility and speed in the testers themselves. So, the ideal test instrument for the RF space would allow for quick reuse of both transmit and receive digital signal processing (DSP) algorithms and also be highly performant and flexible.
The traditional approach to these sorts of testers has been to create a fixed-function instrument crafted to measure and test a specific category of communications. To truly converge design and test, not only does the test process, test bench, and collateral need to be pulled forward into the design flow, but in the ideal sense, the design and tests could execute not in simulation, but rather directly with real-world hardware and real-world signals. In the case of LabVIEW and the NI VST vector signal transceiver, once the DSP building blocks of a communication stream are defined and executing as functionally expected on a desktop, the designer can retarget their algorithm from their desktop design environment to the vector signal transceiver running on its FPGA.
Figure 2. The architecture of the NI VST vector signal transceiver allows for user-modifiable DSP blocks to be simulated and deployed on either the host or firmware of the device. The other input/output and memory interfaces are also available for modification to complement the algorithm design.
A key element of this migration and a common stumbling block in the transition from algorithm design to final deployment (either for the design itself or the tester), is the proper integration of real-world time and, more importantly, hardware I/O and signal calibration. Traditionally, for both design and test functions, the DSP algorithm designer is distinct from the team that would implement device firmware including I/O integration. With the vector signal transceiver and LabVIEW RIO programmable devices like it, NI provides a reprogrammable, and thus very flexible, RF hardware platform with highly optimized IP blocks. These blocks manage the standard complexities of high-speed A/D and D/A integration with signal calibration as well as DMA streams of data to host processors and high-speed onboard memory. This IP, included with the vector signal transceiver, addresses three fundamentally important characteristics. First, it functionally simulates on the desktop so it can be used during algorithm design. Second, the source code is available for reference or modification as needed. And finally, as stated previously, it migrates smoothly to actual real-time execution.