Figure 1. The 5G Ecosystem (Source: 5GPPP, Why the EU is betting big on 5G, 2015)
Challenges in Determinism
Applications such as 5G New Radio (5G NR) introduce timing constraints that make the relationship between the processor and RF front end even more critical than previous communication protocols like LTE or 802.11. Ultra-reliable machine type communication creates a need for upper-layer functionality to occur in much more deterministic and precise timing intervals, which forces technologies like schedulers to be implemented more deterministically. New 802.11 standards such as 802.11ax depend on strict timing requirements as access points determine channel models dynamically through trigger frames and a trigger-based physical layer protocol data unit (PPDU). All these interactions must happen in tight 16us timing requirements, otherwise the communication breaks down. Determinism is becoming increasingly necessary in applications as more and more intelligence is provided to the PHY layer through a MAC. Time-critical operations can no longer be implemented strictly with a PC. Technologies like real-time OSs and FPGAs must be used to handle these sub-1ms timing requirements.
Challenges in Processing
In increasing processing power, there are always difficulties such as the mobility of a processing unit, data pipes that transition data from processing resource to processing resource, and the flexibility of the configuration. With complex developments in MAC layer functionality, added focus on software-defined networks, and more robust and complex schedulers, the need for time-accurate processing and parallel computing becomes greater.
Let’s specifically explore the software-defined networking case. With complex requirements from a software-defined communication network, any node may need to completely reconfigure its function at short notice. Integrating a single node with the processing power to handle those decision-making tasks requires transceivers to scale beyond the RF. The RF node may need to have either the ability to process decisions from a scheduler at a central processing point or run its own decision engine, which both require advancements in processing that scales beyond typical ASICs.
However, raw processing power is still not enough. As the need for environment emulation grows, whether from the channel, base station, or user equipment perspective, increasingly lower latencies between processor and circuitry are required. Any application that integrates heterogenous processor architectures (GPP, GPU, FPGA, and so on) requires that the data be transferred over high-speed serial interfaces with low latency and wide data bandwidth.
Figure 2. Network Diversification—Remote Radio Heads and Device-to-Device Communications Increase Network Complexity
Challenges in Scale
It's no surprise that technology is shrinking, whether looking at the trend of the off-the-shelf device side of technology or the silicon that the devices are built with. The technology is not only shrinking but it's also changing scale. Instead of the base station of old, multiple deployed radio nodes may act as the new infrastructure for 5G and beyond. This introduces an entirely new range of needs including servicing the infrastructure and implementing software updates remotely.
However, these changes affect more than operators. Wireless communications researchers must be able to move out of the lab and into the field for real-world trials. The technology can no longer just be demonstrated at the lab level. Multiple universities, operators, and vendors are collaborating to deploy testbeds throughout cities to demonstrate the capabilities of new physical, data link, and network layers in a real-world environment. Deploying hardware for field trials and maintaining accessibility to the project from remote campuses introduce a variety of new issues.
The Stand-Alone USRP RIO: USRP-2974
The USRP (Universal Software Radio Peripheral) solution has been the benchmark of industry and academic software defined radio (SDR) technology for the past decade.
Figure 3. USRP-2974
The USRP-2974 is the first stand-alone SDR from NI and will be the first NI USRP to use the power of LabVIEW software, the LabVIEW FPGA Module, and the LabVIEW Real-Time Module, all in a single device. It is designed around the existing USRP RIO hardware solution, but now integrates an x86 processor connected to the USRP through high-speed PCI Express and Ethernet connections for data streaming between an x86 target and FPGA target.
An x86 processor that’s incorporated into the design of an SDR provides many benefits. First, the LabVIEW Real-Time programmable processor is now the ideal target to test scheduler algorithms, allowing for prioritization on the processor and deterministically operating on and sending commands to the FPGA, which in turn can handle the physical layer RF signals. Second, because data can be processed onboard the device, every radio node can run additional computation beyond what previously was done on only the FPGA. Finally, with an Ethernet connection to a development machine, any number of USRP-2974 devices can be deployed with duplicate or unique code bases in a flash, which improves system and code management at the individual module level or at the large-scale testbed.
The USRP-2974 opens the doors for new research and advanced use cases previously limited by traditional SDRs. Systems become more scalable, are more easily managed, and can now integrate decision making and deterministic selection through the onboard processor. The USRP-2974 provides the high performance to tackle even the most complex of communications challenges.