Critical Security Update

To help protect your systems, customers using NI driver software 2026 Q2 or earlier should visit ni.com/ni-pal-update and follow the recommended actions.

NI-SmartNIC 2026 Q1 Bug Fixes

Created Feb 3, 2026

Overview

The following items are notable issues fixed between the release of NI-SmartNIC 2025 Q4 and NI-SmartNIC 2026 Q1, including additional patches and service packs. If you have an issue ID, you can search this list to validate that the issue has been fixed. This is not an exhaustive list of issues fixed in the current version of NI-SmartNIC.

Glossary of Terms

Bug Number	Legacy ID	Description	Details
3398299		PXIe-8290 operates at incorrect clock rates when set to operate at 175 MHz When using the MgtReferenceClockRates property exposed through the System Configuration API by the PXIe-8290, passing a value of 175 MHz will incorrectly configure the clocking chip to generate a 306.25 MHz MGT reference clock instead of the expected 175 MHz. In an FPGA design using Aurora IP that expects a 175 MHz reference clock, this will cause the PLL to fail to lock and the Aurora links will fail to come up. Workaround: There is no workaround to configure the MGT reference clock for 175 MHz. If the FPGA design can tolerate other MGT reference clock rates, a workaround is to set the MgtReferenceClockRates property to another supported value (156.25 MHz or 312.5 MHz).	Reported Version: NI-SmartNIC: 2025 Q4 Resolved Version: NI-SmartNIC: 2026 Q1 Added: Oct 22, 2025

Bug Number

Legacy ID

Description

Details

3398299

PXIe-8290 operates at incorrect clock rates when set to operate at 175 MHz

When using the MgtReferenceClockRates property exposed through the System Configuration API by the PXIe-8290, passing a value of 175 MHz will incorrectly configure the clocking chip to generate a 306.25 MHz MGT reference clock instead of the expected 175 MHz. In an FPGA design using Aurora IP that expects a 175 MHz reference clock, this will cause the PLL to fail to lock and the Aurora links will fail to come up.

Workaround:

There is no workaround to configure the MGT reference clock for 175 MHz. If the FPGA design can tolerate other MGT reference clock rates, a workaround is to set the MgtReferenceClockRates property to another supported value (156.25 MHz or 312.5 MHz).

Reported Version:

NI-SmartNIC: 2025 Q4

Resolved Version:

NI-SmartNIC: 2026 Q1

Added:

Oct 22, 2025

Additional Patch Information

Installing some patches may require certain additional steps or considerations. Please refer to the following table for more information about patches for this release.

These patches currently do not have any special instructions.

Glossary of Terms

Bug ID - When an issue is reported to NI, you may be given this ID or find it on ni.com. You may also find IDs posted by NI on the discussion forums or in KnowledgeBase articles.
Legacy ID – An older issue ID that refers to the same issue. You may instead find this issue ID in older known issues documents.
Description - A few sentences which describe the problem. The brief description given does not necessarily describe the problem in full detail.
Workaround - Possible ways to work around the problem.
Reported Version - The earliest version in which the issue was reported.
Resolved Version - Version in which the issue was resolved or was no longer applicable. "N/A" indicates that the issue has not been resolved.
Date Added - The date the issue was added to the document (not the reported date).