NI-SmartNIC 2025 Q3 Known Issues

Updated Jul 25, 2025

Overview

This document contains the NI-SmartNIC known issues that were discovered before and since the release of NI-SmartNIC 2025 Q3. Known issues are performance issues or technical bugs that NI has acknowledged exist within this version of the product.

Not every issue known to NI appears on this list; it is intended to show the most severe and common issues that you may encounter and provide workarounds when possible. Other technical issues that you may encounter could occur through normal product use or system compatibility issues. You may find more information on these issues in NI’s Product Documentation, Knowledgebase, or Community; see Additional Resources.

Glossary of Terms

Bug Number	Description	Details
3162256	Compiling FPGA bitfiles using AMD Vivado scripts will fail with "DRC INBB-3" error After generating intermediate files, when compiling an FPGA bitfile for PXIe-8290 using AMD Vivado scripts the compile fails with a "DRC INBB-3 black box" error. Workaround: This issue can occur because of limited file permissions for the user executing the Vivado compile script which can prevent being able to write output files into their default directory. This can be avoided by changing the output directory of the generated scripts. After generating intermediate files, go to where they were generated. Under ".../src/gen/..." modify both AuroraFramingGtm.bd and AuroraFramingGtyp.bd, Where is says "gen_directory": "../../../../VivadoProject" remove two "../" from the relative path. The result should look something like "gen_directory": "../../VivadoProject" You should now be able to run a Vivado build without error.	Reported Version: NI-SmartNIC: 2025 Q3 Resolved Version: N/A Added: Jul 21, 2025
3190691	niFpgaGenerateLvbitx.vi missing from PXIe-8290 FPGA project folder After compiling the FPGA project with Vivado finishes, the niFpgaGenerateLvbitx.vi script to convert the .pdi output from Vivado to a .lvbitx is missing. Workaround:* Once the build is finished, manually copy niFpgaGenerateLvbitx.vi in order to convert your pdi to an lvbitx. This vi gets installed into LabVIEW itself. ex. for LabVIEW 2025 "[LV2025DIR64]vi.lib\rvi\CDR\niFpgaGenerateLvbitx.vi" Copy this vi next to your SleipnirTop.pdi from the Vivado build and run it. This should produce SleipnirTop.lvbitx	Reported Version: NI-SmartNIC: 2025 Q3 Resolved Version: N/A Added: Jul 21, 2025
3190657	PXIe-8290 example project hangs in execution When running the PXIe-8290 Aurora example, the top level host VI hangs when waiting for the PLL lock. Workaround: Move the IO Node Write of xFF to GtPowerGoodIn to occur before the loop that waits for aGTPllLocked.	Reported Version: NI-SmartNIC: 2025 Q3 Resolved Version: N/A Added: Jul 21, 2025

Bug Number

Legacy ID

Description

Details

3162256

Compiling FPGA bitfiles using AMD Vivado scripts will fail with "DRC INBB-3" error

After generating intermediate files, when compiling an FPGA bitfile for PXIe-8290 using AMD Vivado scripts the compile fails with a "DRC INBB-3 black box" error.

Workaround:

This issue can occur because of limited file permissions for the user executing the Vivado compile script which can prevent being able to write output files into their default directory. This can be avoided by changing the output directory of the generated scripts.

After generating intermediate files, go to where they were generated.
Under ".../src/gen/..." modify both AuroraFramingGtm.bd and AuroraFramingGtyp.bd,
- Where is says "gen_directory": "../../../../VivadoProject" remove two "../" from the relative path.
- The result should look something like "gen_directory": "../../VivadoProject"
You should now be able to run a Vivado build without error.

Reported Version:

NI-SmartNIC: 2025 Q3

Resolved Version:

N/A

Added:

Jul 21, 2025

3190691

niFpgaGenerateLvbitx.vi missing from PXIe-8290 FPGA project folder

After compiling the FPGA project with Vivado finishes, the niFpgaGenerateLvbitx.vi script to convert the *.pdi output from Vivado to a .lvbitx is missing.

Workaround:

Once the build is finished, manually copy niFpgaGenerateLvbitx.vi in order to convert your pdi to an lvbitx.

This vi gets installed into LabVIEW itself. ex. for LabVIEW 2025 "[LV2025DIR64]vi.lib\rvi\CDR\niFpgaGenerateLvbitx.vi"
Copy this vi next to your SleipnirTop.pdi from the Vivado build and run it. This should produce SleipnirTop.lvbitx

Reported Version:

NI-SmartNIC: 2025 Q3

Resolved Version:

N/A

Added:

Jul 21, 2025

3190657

PXIe-8290 example project hangs in execution

When running the PXIe-8290 Aurora example, the top level host VI hangs when waiting for the PLL lock.

Workaround:

Move the IO Node Write of xFF to GtPowerGoodIn to occur before the loop that waits for aGTPllLocked.

Reported Version:

NI-SmartNIC: 2025 Q3

Resolved Version:

N/A

Added:

Jul 21, 2025

Final Time Issue Listed

Issues found in this section will not be listed in future known issues documents for this product.

There are currently no issues to list.

Additional Resources

Explore Support Content and Product Documentation

Ask the NI Community

Request Support from an Engineer

A valid service agreement may be required, and support options vary by country

Glossary of Terms

Bug ID - When an issue is reported to NI, you may be given this ID or find it on ni.com. You may also find IDs posted by NI on the discussion forums or in KnowledgeBase articles.
Legacy ID – An older issue ID that refers to the same issue. You may instead find this issue ID in older known issues documents.
Description - A few sentences which describe the problem. The brief description given does not necessarily describe the problem in full detail.
Workaround - Possible ways to work around the problem.
Reported Version - The earliest version in which the issue was reported.
Resolved Version - Version in which the issue was resolved or was no longer applicable. "N/A" indicates that the issue has not been resolved.
Date Added - The date the issue was added to the document (not the reported date).