The following items are notable issues fixed between the release of FlexRIO 2025 Q2 and FlexRIO 2025 Q3, including additional patches and service packs. If you have an issue ID, you can search this list to validate that the issue has been fixed. This is not an exhaustive list of issues fixed in the current version of FlexRIO.
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Bug Number |
Legacy ID |
Description |
Details |
|---|---|---|---|
| 2051624 |
NI-148X Getting Started Example Has a Broken VIThe 148X getting started example has a broken VI: <lvdir>\ProjectTemplates\Source\FlexRIO\NI148X\Getting Started\Host\Common\API\Display Images.vi. The VI displays an error message - "The refnum that is being passed into this node is not fully defined." Workaround: Removing and rewiring the purple 'display images' wire will fix the broken run arrow. |
Reported Version: FlexRIO: 2022 Q3 Resolved Version: FlexRIO: 2025 Q3 Added: Aug 16, 2022 |
|
| 939637 |
Compiling a bitfile with the NI 6589 Serdes CLIP will fail with error Initialization time cannot be greater than 49 msThe Connector Serdes and Channel Serdes CLIPs for the 6589 all have incorrect lower frequency ranges for the CLIP clocks: Acq Regional, Gen Regional and PFI Regional. The lower frequency is 1 Hz - if you try to compile with that frequency LabVIEW throws error 61499 during code gen: "LabVIEW FPGA: An internal software error in the LabVIEW FPGA Module has occurred. Please contact National Instruments technical support at ni.com/support.
Additional Information: Initialization time cannot be greater than 49 ms." Workaround: - Open LabVIEW - Go to NI 6589 Examples o If you want to work with <Serdes Channel> in your future application, Select: NI 6589 Serial Generation - Export Clock o If you want to work with <Serdes Connector> in your future application, Select: NI 6589 Finite Acquisition - External Clock Start Trigger - ! NEVER Right Click on the IO Module and Select Properties! - Remove Unused FPGA Targets from Project and create a *.zip file of entire Project and save it somewhere you prefer - Open up the Example VI and change it to preferred Code - Generate Intermediate Files, Build Bitfile - Create a New Project (Referring as your Application Project) - Add your physical Target 7975R - Enable NI 6589 Module, Select Serdes Connector - On Host Vi, Right Click on <Configure FPGA Reference> and Choose the compiled FPGA bitfile from the other project |
Reported Version: FlexRIO: 19.1 Resolved Version: FlexRIO: 2025 Q3 Added: Aug 16, 2022 |
|
| 2242884 |
PXIe-1486 and 1487 unable to perform I2C Tap Passthrough on Channels 1 and 2 with GSEDue to a known issue in the getting started example the PXIe-1486 and 1487 are unable to perform I2C Tap Passthrough with Channels 1 and 2.
Workaround: Please reach out to NI support for assistance in a workaround.
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Reported Version: FlexRIO: 2022 Q3 Resolved Version: FlexRIO: 2025 Q3 Added: Feb 21, 2023 |
|
| 2296986, 2348644 |
PXIe-7903 or PXIe-6954 will fail to compile a bitfile if LabVIEW is not run in administrator modeWhen run from LabVIEW without administrator privileges, PXIe-7903 or PXIe-6954 FPGA applications will fail to compile bitfiles in the codegen step due to permissions error copying files to the lvaddons directory.
Workaround: Run LabVIEW in Administrator mode when compiling bitfiles.
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Reported Version: FlexRIO: 2023 Q1 Resolved Version: FlexRIO: 2025 Q3 Added: Oct 12, 2023 |
Installing some patches may require certain additional steps or considerations. Please refer to the following table for more information about patches for this release.
These patches currently do not have any special instructions.