Before discussing synchronization, it is helpful to first understand the different clocks present in M Series devices. The NI-STC 2 timing and controller ASIC on M Series devices generates several timebases by dividing down an 80 MHz timebase. This 80 MHz timebase is derived in one of two ways – either from the 80 MHz onboard oscillator or from the phase-lock-loop (PLL) circuit , as shown in Figure 1 below. When the reference clock for the PLL is shared among devices, the 80 MHz timebase produced from the PLL will be synchronized among those devices. Thus, all the clocks derived from that 80 MHz timebase or the resulting 20 MHz timebase will also be synchronized. Due to the way signals are divided, the 100 kHz timebase will not be in phase with the input to the PLL. These timebase signals are used internally as clock sources for the analog input, analog output, and counter/timers subsystems of the device. For example, the analog input subsystem will divide down one of these timebases to create its AI Sample Clock. From this 80 MHz onboard oscillator, each M Series device also generates its own 10 MHz reference clock, which can be used for synchronization in a multidevice system.
Figure 1 Clock Routing Circuitry of an M Series Device
Sample clocks for analog operations on M Series devices are typically obtained by dividing down either the 20 MHz or 100 kHz internal timebase. The counter/timers are the only subsystem that can directly use the 80 MHz timebase. It is also possible to source other external and internal signals such as the PXI_STAR trigger, analog comparison event, or signals from PFI lines or the RTSI bus. For more information about AI and AO sample clock derivation, read the timing signal sections of the M Series User Manual .