The LabVIEW host code acts as the user interface used to communicate with the FPGA. The host code interacts directly with the FPGA code by updating controls and reading from indicators on the front panel of the FPGA code. This functionality is supported by the NI-RIO driver.
This example personality consists of three main steps:
1. Open a reference to the FPGA bitfile on the R Series target.
2. Use a Read/Write Node to update controls and indicators on the FPGA front panel.
3. Close the reference to the FPGA bitfile.
See the example host block diagram in Figure 6.
Figure 6. Block Diagram of the LabVIEW Host Code
These three main steps describe the overall setup of the host VI. This host code is a little more complex because of conversions that must take place prior to writing to a control. The following sections explain these three main steps in more detail.
1. Open Reference to Target FPGA
Figure 7. First Part of the Host Code
The first part of the code is the initialization stage. In this part, the resource name for the target R Series board is passed to the Open FPGA VI Reference. This function opens a reference to the board that can be used by any subsequent functions or subVIs that communicate with the FPGA. The reference is then passed to the Read/Write Node and the digital lines are initialized to function as an output or input. Finally, the Invoke Method Node is used to start the FPGA code on the R Series board.
2. Read FPGA Indicators and Write to FPGA Controls
Figure 8. Middle Part of the Host Code
The middle part of the code consumes the majority of the execution time for this host VI. This part of the code consists of a While Loop with a Read/Write Node inside of it. The Read/Write Node gives users the ability to write to controls and read from indicators on the front panel of the FPGA code. In Figure 8, each input to the node is a control in the FPGA code.
For example, Output 0 – Low Time (Ticks) is the name of a control in the FPGA code. This particular control defines how many ticks DIO line 0 will output a low value. That control paired with Output 0 – High Time (Ticks) defines a PWM output channel (the high time and low time correlate to a frequency and duty cycle). Refer to Figure 1 to see these controls being used on the FPGA.
While LabVIEW FPGA supports fixed-point and floating-point data types, integer data types are the most efficient to use when it comes to consuming FPGA resources. For this reason, the data type written to the FPGA code is an integer (in this case it is a U32) and any division necessary is done on the host. The intermediate subVI, FreqtoPulse, converts the desired frequency and duty cycle for a PWM output channel to a low time and high time represented in ticks.
The While Loop executes at a rate defined by the Wait Until Next ms Multiple function. In this case, the user has defined the wait as 100 ms. This means that the While Loop executes every 100 ms, or at a rate of 10 Hz.
3. Close the FPGA Reference
Figure 9. Final Part of the Host Code
The final part of the host VI closes the reference to the R Series board. It also handles any errors that occurred during the execution of the host VI.
The host code front panel layout is in a quadrant form. PWM is on the left, DIO is on the right, outputs are on the top, and inputs are on the bottom. Figure 10 shows the front panel.
Figure 10. Front Panel of the LabVIEW Host Code