High-Throughput LabVIEW FPGA Course

The High-Throughput LabVIEW FPGA course teaches you the essential skills and processes to become proficient at designing high-performance applications with LabVIEW FPGA. During this course, you will learn about FPGA hardware resources and how LabVIEW code maps to these resources. You will review case studies, architectural considerations, and simulations to learn NI recommended design flow when implementing large FPGA applications.

Course Details:

High-Throughput LabVIEW FPGA Course Outline

Lesson Overview Topics
Graphical Design in LabVIEW FPGA The goal of this section is to provide insight into FPGA hardware resources and how LabVIEW code maps to these resources in terms of size and propagation delay/loop rate
  • Introduction to FPGAs 

  • Mapping LabVIEW primitives to FPGA resources 

  • Execution time/propagation delay/critical path/loop rate/clock rate 

  • Throughput

Host Communication with LabVIEW FPGA through NI-RIO This lesson covers the methods of interacting between host and FPGA VIs
  • Memory-mapped register access 

  • DMA 

  • Interrupts 

  • Interactive and programmatic FPGA VI execution

I/O in LabVIEW FPGA There are many methods of connecting the LabVIEW FPGA VI to other logic on the FPGA as well as I/O outside the FPGA.
  • Socketed CLIP 

  • Importing HDL into CLIP 

  • Target I/O 

  • Synchronous and asynchronous I/O 

  • Metastability and glitching, synchronization registers

Crossing FPGA Clock Domains Large applications often involve logic running at multiple rates. There are specific considerations for exchanging data between these “clock domains.”
  • Use cases for multiple clock domains 

  • Global and Local Variables 

  • Handshaking 

  • FIFOs 

  • 2- and 4-wire handshaking introduction 

  • Memory items

LabVIEW FPGA Algorithm Design - DSP Case Study To illustrate the NI recommended design flow, this lesson presents a case study on DSP design.  
  • Recommended FPGA design flow 

  • FIR filter introduction 

  • Behavioral and structural models 

  • IP sources 

  • Fixed-point math 

  • Test benches 

  • Dataflow-accurate FPGA simulation 

  • Algorithm implementation options 

  • Balancing performance and portability 

  • Integrating IP with the IP Integration Node 

  • Comparison of the IP Integration Node and the CLIP Node 

  • Xilinx IP palette 

  • Hardware test

LabVIEW FPGA Algorithm Design - Digital Protocol Case Study To illustrate the NI recommended design flow, this lesson presents a case study on digital protocol implementation.  
  • Recommended FPGA design flow 

  • State machine theory 

  • State machines in LabVIEW

High-Throughput LabVIEW FPGA Course Outline  
  • State machine execution timing 

  • SPI protocol introduction 

  • Test benches 

  • Dataflow-accurate FPGA simulation 

  • Hardware test                                                              

  • Digital Debouncing 

  • Bit Error Rate Test (BERT) 

  • FPGA resets

LabVIEW FPGA Architectures There are additional architectural considerations when building large FPGA applications. This section covers a design from concept to implementation.
  • Concept to Implementation design flow 

  • Throughput requirements 

  • Storage requirements 

  • Clocking architecture 

  • Communication policies 

  • Case study on an FPGA-based multi-record averager and FFT                

  • Best practices for large FPGA designs

Simulation and Debug of FPGA Designs with Third-Party Tools While most designs can be simulated with sufficient fidelity in LabVIEW, for completely bit-true, cycle accurate simulation, some designs may require a third-party cycle-accurate simulator.
  • Overview of cycle-accurate simulation 

  • Simulation in Mentor Graphics ModelSim and Xilinx Isim 

  • VHDL test benches 

  • Co-simulation with LabVIEW 

Get started with High-Throughput LabVIEW FPGA today