The LabVIEW NXG FPGA Module is the next generation of LabVIEW FPGA and contains only a subset of the features and hardware support in the LabVIEW 2020 FPGA Module. Use the comparison chart to determine which version is right for your next project.
| LabVIEW 2020 FPGA Module | LabVIEW NXG FPGA Module 5.0 | |
|---|---|---|
| Explore the Product |
Download Evaluation |
Download Evaluation |
| Hardware | ||
| USRP-2940/2942/2943/2944/2950/2952/2953/2954 | ||
| USRP-2974 | — | |
| USRP-29x5 (TwinRX) | — | |
| Ettus Research USRP B2x0, USRP N210 | ||
| Ettus Research USRP X310 | ||
| FlexRIO PXIe-797x (Kintex-7) + Select FAMs | ||
| FlexRIO PXIe-576x/791x (UltraScale) | — | |
| ATCA-3671 | — | |
| C-Series Modules | Partial | |
| CompactRIO Systems | Partial | |
| Reconfigurable I/O Modules and Devices (R Series) | — | |
| PXI High-Speed Serial Instruments | — | |
| PXI Vector Signal Transceivers | — | |
| myRIO Student Embedded Device | — | |
| Programming Environment | ||
| SystemDesigner | — | |
| FPGA Resource Collection | — | |
| Interactive Front Panel Communication | — | |
| Clock-Driven Logic (Including Single-Cycle Timed loops) | ||
| Standard loops structures (not using Clock-Driven logic) | ||
| Programming Structures | ||
| Data Communications and Storage | ||
| Classes | ||
| FPGA Instrument Design Libraries | Partial | |
| Sampling Probes | ||
| Advanced Sampling Probes | — | |
| Linear Algebra | ||
| FPGA Math | ||
| Third-Party Software Interoperability and Code Integration | ||
| Xilinx IP | ||
| Integrate VHDL—IP Integration Node | ||
| Integrate VHDL—User-Defined CLIP | ||
| Integrate VHDL—Socketed CLIP | Partial | |
Initially Supporting Voltage Input Modules (9201,9205, 9206, 9221); Current Input Modules (9203); Voltage Output(9263,9264,9269); Current Output (9265,9266); Digital (9401)
LabVIEW NXG FPGA Module supports CompactRIO with DAQmx systems, which include the 904x and 905x models.
The LabVIEW Communications System Design Suite enables to quickly build a wireless communications prototype.
Configure all your FPGA resources, such as FIFOs, clocks, and memory, in one document and quickly reuse them on multiple targets.
In LabVIEW NXG FPGA, Single-Cycle Timed Loops are called Clock-Driven Loops.
Does not include all features of standard while loops, such as base clock configuration.
LabVIEW NXG currently has the Basic Elements, Data Trigger, and Streaming libraries.
View wire values in simulation on a clock-cycle-by-cycle basis. Includes support for arrays and clusters.
Requires guidance from NI support. Open a service request for assistance.
FlexRIO 18.5.1 provides support for the following FlexRIO Adapter Modules in the LabVIEW NXG FPGA Module: