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Figure 1. FPGA Carrier Block Diagram Synchronization Gen3 x8 PCIe FPGA DRAM Bank 1 +12 V I/O Module Mezzanine Connector DIO Connector Flash Power Supplies +12 V, +3.3 V PXIe Backplane Module Clocking MGTs ...

Use Measurement & Automation Explorer (MAX) to configure your NI hardware. MAX informs other programs about which NI hardware products are in the system and how they are configured. MAX is automatically ...

FlexRIO examples are available in LabVIEW's NI Example Finder. Complete the following steps to access the examples by task. In LabVIEW, click Help » Find Examples . In the NI Example Finder window that ...

The LabVIEW FPGA Module includes component-level intellectual property (CLIP) for HDL IP integration. FlexRIO devices support two types of CLIP: user-defined and socketed.

Table 1. FlexRIO Documentation and Resources Document/Resource Location Description PXIe-6593 Getting Started Guide (this document) Available at ni.com/manuals . Contains installation instructions and ...

FlexRIO includes several example applications for LabVIEW. These examples serve as interactive tools, programming models, and as building blocks in your own applications. Parent topic: Getting Started ...

Figure 1. PXIe-6593 Front Panel PXIe-6593 FlexRIO Serial Digital DIO 16.3 Gbps REF/ CLK IN CLK OUT 4 Vpp MAX PORT 0 PORT 1 Connector Description Function DIO Molex Nano-Pitch DIO connector Multi-signal ...

This document explains how to install, configure, test, and use the PXIe-6593 . You can program the PXIe-6593 with the following software options. FlexRIO driver software NI LabVIEW Instrument Design Libraries ...

In the MAX configuration tree, expand Devices and Interfaces . Expand the Chassis tree to see the list of installed hardware, and press to refresh the list. If the module is still not listed, power ...

Notice To prevent damage to the PXIe-6593 caused by ESD or contamination, handle the module using the edges or the metal bracket. Ensure the AC power source is connected to the chassis before installing ...

Before installing your hardware, you must install the application software and instrument driver. Install the software in the following order: Install LabVIEW. Refer to the LabVIEW Installation Guide for ...

Restart the system. Launch MAX, and perform the self-test again. Power off the chassis. Reinstall the failed module in a different slot. Power on the chassis. Perform the self-test again. Parent topic: ...

Visit ni.com/support to find support resources including documentation, downloads, and troubleshooting and application development self-help such as tutorials and examples. Visit ni.com/services to learn ...

To use the PXIe-6593 , your system must meet certain requirements. For more information about minimum system requirements, recommended system, and supported application development environments (ADEs), ...

If an issue persists after you complete a troubleshooting procedure, search our KnowledgeBase for additional information our technical support engineers create as they answer common user questions and ...

Notice To prevent electrostatic discharge (ESD) from damaging the device, ground yourself using a grounding strap or by holding a grounded object, such as your computer chassis. Touch the antistatic package ...

The following items are included in the device kit: PXIe-6593 Documentation: PXIe-6593 Getting Started Guide (this document) PXIe-6593 Safety, Environmental, and Regulatory Information Parent topic: Getting ...

Definitions Warranted specifications describe the performance of a model under stated operating conditions and are covered by the model warranty. Characteristics describe values that are relevant to the ...

This is the Letter of Volatility for the PXIe-6593.

This page documents all the applicable standards and certifications for the PXIe-6593 and provides downloadable certifications.

Before you begin, you must install the necessary Xilinx compilations tool for Vivado on the local computer to export an FPGA VI as a Vivado Design Suite project or open the exported project. Note If you ...

LabVIEW FPGA does not support Verilog source files in CLIP. But, you can generate EDIF netlists from any synthesized Verilog components in the IP you are using and instantiate the netlist in a VHDL wrapper ...

If your application will not use Aurora Core IP, you can choose to purchase or license third-party IP. Follow the guidelines below to optimize your third-party IP for LabVIEW integration. When Generating ...

Place an FPGA I/O node on the FPGA target block diagram. The FPGA I/O node is located on the palette under Functions»FPGA I/O»FPGA I/O Node . Right-click the FPGA I/O node and select Add New FPGA I/O . ...

You can include all CLIP-specific user constraints, except pin placement constraints, in the constraints file (.xdc) you will add to your LabVIEW project. Complete the following steps to apply constraints ...

The PXI FlexRIO High-Speed Serial Instruments require you to develop an FPGA VI, design a socketed CLIP (Component Level IP), and compile a LabVIEW bitfile that implements a custom high-speed serial protocol. ...

Create a new project by selecting File»New»Project , or open an existing project by selecting File»Open . Right-click My Computer in the Project Explorer window and select New»Targets and Devices . In ...

To debug link connections in your FlexRIO high-speed serial application, use the Eye Scan API located on the NI Eye Scan palette at FPGA Interface»Software-Designed Instrument»NI High-Speed Serial»NI Eye ...

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