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Skip to Content BookmarksWatch ListSearch PreferencesLog in NI FlexRIO FPGA Module Installation Guide and Specifications • Last Updated: 2022-04-30 • Tags:  ○ Getting Started ○ PXIe-7976 ○ PXIe-7975 ○ ...

In order to compile your LabVIEW FPGA code for your NI FPGA Hardware (RIO, R Series etc) locally or use features of LabVIEW FPGA that require a local installation of the compile tools, you will need the ...

This is the Letter of Volatility for the PXI-795x and PXIe-796x.

This page documents all the applicable standards and certifications for the PXI-7952 and provides downloadable certifications.

You can use an Invoke Method function to invoke an action from the host VI to the FPGA VI with this device. The host VI is available from the LabVIEW FPGA host interface. The Invoke Method function is ...

This memory interface provides the highest performance interface to external DRAM. Both the write-side and read-side data ports are exposed as 64-bit data words. Requests to write to and read from DRAM ...

Figure 1. FPGA I/O Node You can use an FPGA I/O Node, configured for reading and writing, with the your FlexRIO Modular I/O FPGA Module. The FPGA I/O Node is located on the FPGA I/O Functions palette and ...

Arbitration —This device supports arbitration to determine which object can access the resource if multiple objects request access at the same time. Configure the arbitration settings for the channels ...

Use the FPGA memory item interface to use DRAM in the same way that you use block memory and look-up tables (LUT). DRAM memory items appear in the Project Explorer window under the FPGA target. The FPGA ...

Use the socketed CLIP interface to communicate directly with the onboard DRAM. Socketed CLIP lists all memory interfaces that are compatible with the selected DRAM bank item.

The DRAM interface signals are synchronous to the DRAM interface clock. Synchronization registers cause a delay in sending and receiving data or commands to and from the DRAM interface. For proper device ...

The access size is the amount of information stored in one memory address. You can set up memory to use a variety of data types. To achieve the best performance and to utilize the maximum amount of data, ...

Some FlexRIO devices contain onboard DRAM that is directly accessible from the FPGA VI. LabVIEW supports two types of DRAM interfaces: FPGA memory items and socketed CLIP. You cannot use both FPGA memory ...

FlexRIO devices have different memory interfaces that provide access to the external DRAM memory. When you enable the DRAM memory bank in the DRAM General Properties dialog box, any compatible memory interfaces ...

Memory items that are assigned to the same bank cannot access the DRAM simultaneously. Access to the DRAM is controlled by a grant time that dictates when a memory item can read or write to the DRAM bank, ...

There is a long latency between data requests and the execution of the requests due to the pipeline of the DRAM architecture. Therefore, NI recommends creating your design with a “look ahead” approach. ...

DRAM is optimized for high storage density and high bandwidth. DRAM accesses data sequentially and in large blocks. For example, you have to read the data in address 0x1 after you have read the data in ...

This memory interface provides the easiest-to-use FIFO interface to external DRAM. The FIFO is exposed as separate read and write interfaces. Both the write-side and read-side data ports are 64-bit data ...

Use the FPGA I/O Method Node to invoke a method on an I/O item or hardware under an FPGA target. The I/O Method Node is located on the FPGA I/O Functions palette. You can use the following methods with ...

This memory interface provides the highest performance interface to external DRAM. Both the write-side and read-side data ports are exposed as 128-bit data words. Requests to write to and read from DRAM ...

You can use an FPGA I/O Node, configured for reading and writing, with this device. The FPGA I/O Node is located on the FPGA I/O Functions palette and performs specific FPGA I/O operations on your FPGA ...

You can use an FPGA I/O Node, configured for reading and writing, with this device. The FPGA I/O Node is located on the FPGA I/O Functions palette and performs specific FPGA I/O operations on your FPGA ...

Arbitration —This device supports arbitration to determine which object can access the resource if multiple objects request access at the same time. Configure the arbitration settings for the channels ...

Arbitration —This device supports arbitration to determine which object can access the resource if multiple objects request access at the same time. Configure the arbitration settings for the channels ...

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