The hardware elements above combine to form a testbed that can scale from a few antennas to more than 128 synchronized antennas. For simplicity, this paper uses a 128-antenna configuration in each diagram.
High-channel-count MIMO systems require exceptionally robust data processing. Up to 128 channels of I and Q samples must be processed in real time for both transmit and receive. To handle this amount of data, the MIMO Prototyping System uses high-throughput PCI Express buses. Data is sent from the USRP RIO SDRs through PCI Express switch boxes to a single PXI Express chassis. The chassis aggregates data for centralized processing with both FPGA coprocessors and a quad-core Intel i7 PXI controller. As shown in Figure 7, a PXIe-1085 Chassis is the main data aggregation node and real-time signal processing engine. In slot 1 of the chassis, the PXIe-8135 RT Controller acts as a central system computer. The PXIe-8135 RT features a 2.3 GHz quad-core Intel Core i7-3610QE processor (3.3 GHz maximum in single-core Turbo Boost mode). The chassis additionally houses eight PXIe-8384 (S1 to S8) Remote Control Modules to connect the PCI Express switch boxes to the master system. Each switch box in turn aggregates eight USRP RIO connections. The connection between the PXI chassis and the switch boxes uses PCI Express x8 Gen 2 technology to provide up to 3.2 GB/s between the chassis and each switch box.
The system also features PXIe-7976R FlexRIO FPGA coprocessor modules to address the real-time signal processing requirements for the MIMO Prototyping System. Each PXIe-7976R features a powerful Kintex-7 410T FPGA. Each FlexRIO module can receive or transmit data across the backplane to each other and to all the USRP RIO SDRs with <5 µs of latency and up to 3.2 GB/s throughput per FPGA coprocessor. The number of FlexRIO FPGA coprocessors required scales from one to four based on the number of antennas used.
Figure 7. Data Channels in the MIMO Prototyping System
Timing and Synchronization
Proper timing and synchronization are critical in any MIMO system. The MIMO Prototyping System shares a common 10 MHz reference clock and a digital trigger to start acquisition or generation on each radio and ensure system-level synchronization (see Figure 8). The PXIe-6674T Synchronization Module in the chassis uses an OCXO to produce a very stable and accurate 10 MHz reference clock (80 ppb accuracy). It also supplies a digital trigger for device synchronization to the master CDA-2990 clock distribution accessory. The master CDA-2990 then supplies and buffers the 10 MHz reference (MCLK) and trigger (MTrig) to eight additional CDA-2990 modules that feed the USRP RIO SDRs, thereby ensuring that each antenna shares the 10 MHz reference clock and master trigger. As a result, the timing and synchronization architecture offers very precise control of each radio/antenna element. This produces phase-coherent operation, where each channel maintains a constant phase offset from the other channels. You can then use software calibration techniques to sufficiently align the channels.
Figure 8. Clock distribution in the MIMO Prototyping System
Combining the data path hardware with the timing modules produces a powerful testbed that can handle massive flows of data in real time and meet the synchronization needs of MIMO researchers. This system is also inheriently scalable. You can easily add more antennas with only minor changes in the hardware architecture.
Single Antenna UE
In MU-MIMO, a base station with many antennas communicates with several single antenna User Equipment (UE). The MIMO Application Framework supports up to 1 single antenna UEs. Each UE represents a handset or other wireless device. UEs can be represented by using an individual USRP RIO with an internal GPS-disciplined oscillator (GPSDO) connected to a laptop through cabled PCI Express to ExpressCard connection. The GPSDO is important because it provides improved frequency accuracy plus additional synchronization and geo-location capability. A typical MU-MIMO testbed implementation will include multiple USRP RIOs acting independently as UEs. Since each USRP RIO has two RF channels, each USRP and laptop combination can represent two UEs.
Multiple Antenna UE
The MIMO Application Framework supports both single antenna and multiple antenna UEs. UEs can be configured with 1, 2, 4, 6, 8, 10, or 12 antennas. Note that while up to 12 antennas are supported at the UE, the MIMO Application Framework only supports up to 12 spatial streams out of the box. Support for additional spatial streams can be added with modifications to the code base.
For UEs with more than 1 antenna, the required hardware is identical to that of the base station. That is, in addition to the USRP RIO, a PXI chassis, controller, FlexRIO FPGA modules, PXIe-6674T timing and synchronization module, CDA-2990 reference & PPS distribution module, and CPS-8910 PCIe switch box module are also required.