To ensure a seamless transition of algorithms designed in G between processor and FPGA hardware, LabVIEW Communications also provides built-in tools for data-driven float-to-fixed point conversion. Furthermore, the performance optimizations on the implementation are specific to the underlying hardware. For example, for a diagram targeted to the processor, LabVIEW Communications can properly parallelize and partition a design to automatically use the full potential of a multicore processor. If a deterministic execution of such code is needed for a specific application, simply change the hardware target to NI Linux Real-Time without rewriting the code. And for a diagram targeted to the FPGA, it can accept various user-specified constraints like throughput and clock rate to properly synthesize a hardware design on the FPGA fabric.
Overall, this ability to quickly partition the design and rapidly iterate on the ideal implementation is possible with only LabVIEW Communications as it offers access to both the FPGA and processor. As such, without the hardware integration available in the tool, such design flexibility would be nearly impossible to realize. The benefit to users is the ability to better characterize a design and to truly understand design trade-offs, which can motivate further refinements. As legions of researchers join the fray to define the next generations of communications standards, tools that enable efficient, rapid innovation on quality SDR systems are essential in the race to deliver the next disruptive solution to market. It’s no surprise then that LabVIEW Communications System Design Suite and NI SDR hardware are already in the arsenals of those leading the marketplace.
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