This document presents an overview of the I2C (Inter Integrated Circuit) bus, which is commonly used for communication between integrated circuits or sensors. The tutorial discusses the low-level basics of the bus, which includes data transfers, arbitration, and addressing. It also discusses the basic read/write operations and where to find LabVIEW examples and IP. Additional web page links show how to communicate to I2C based devices using the LabVIEW FPGA Module and the I²C/SPI Interface Device from a common programming interface model.
Much information can be found online presenting an overview of I2C. This document explains I2C using LabVIEW. The I2C bus is a two-wire, half-duplex serial interface. The two lines, Serial Data (SDA) and Serial Clock (SCL), are both bidirectional. The I2C specification defines three speeds: standard, 100 kHz; fast, 400 kHz; and high speed, 3.4 MHz.
Each device connected to the I2C bus has a unique 7-bit I2C address to facilitate identification and communication by the master. Commonly, the upper four bits are fixed and assigned to specific categories of devices (for example, 1010 is assigned to serial EEPROMs). The three lower bits are programmable through hardware address pins, allowing up to eight devices of the same type to be connected to a single I2C bus.
Each device on the bus (both master and slave) can be a receiver and/or transmitter. For example, an LCD is typically only a receiver, while an EEPROM is both a transmitter and receiver. Temperature sensors are commonly transmitters in function.
The I2C is a multi master bus, meaning that multiple masters can be connected to the bus at the same time. While a master is initiating a transfer on the bus, all other devices, including other masters, are acting like slaves. However, if another master is trying to control the bus at the same time, I2C defines an arbitration mechanism to determine which master gets control of the bus.
To initiate a transfer, the master issues a start condition by changing the SDA line level from high to low while keeping the SCL clock line high. When this occurs, the bus is considered busy, and all devices on the bus get ready to listen for incoming data.
Next, the master sends the 7-bit address and 1-bit for data transfer direction on the bus to configure for the appropriate data transfer. All slaves compare the address with their own address. If the address matches, the slave produces an ACK (acknowledge) signal.
If the master detects an ACK signal, it starts transmitting or receiving data. To transmit data to a device, the master places the first bit onto the SDA line and generates a clock pulse to transmit the bit across the bus to the slave. To receive data from a device, the master releases the SDA line, allowing the slave to take control of it. The master generates a clock pulse on the SCL line for each bit, reading the data while the SCL line is high. The device is not allowed to change the SDA line state while the SCL line is high.
After the data transmission, the master issues the stop condition by changing the SDA line from low to high while keeping the SCL clock line high. When this occurs, the bus is considered free again for another master to initiate a data transfer.
A device that ACKs must pull down the SDA line during the ACK clock pulse in such a way that the SDA line is stable low during the high period of the ACK related clock pulse. Of course, setup and hold times must be taken into account. During reads, a master must signal an end of data to the slave by NOT generating an ACK bit on the last byte that has been clocked out of the slave. In this case, the slave will leave the data line high to enable the master to generate the Stop condition.
Because the master controls the clock, the I2C specification provides a mechanism to allow the slave to slow down the bus traffic when it is not ready. This mechanism is known as clock stretching. During any SCL low phase, a slave may additionally hold down SCL to prevent it from rising high again to slow down the SCL clock rate or pause I2C communication.
When the master attempts to make SCL high to complete the current clock pulse, it must verify that it has really gone high. If it is still low, it knows a slave is holding it low and must wait until it goes high before continuing.
Typical I2C devices use a 7-bit addressing scheme. I2C also defines an extended 10-bit addressing scheme that allows up to 1,024 addresses to be connected to the I2C bus. This 10-bit addressing scheme does not affect the existing 7-bit addressing, allowing both 7-bit and 10-bit addressed devices to share the bus.
A device that supports 10-bit addressing receives the address across two bytes. The first byte consists of the Philips-designated 10-bit slave addressing mode code (11110), the 2 MSBs of the device address, and the Read/Write bit. The next data byte sent across the bus contains the eight LSBs of the address.
When two masters are trying to control the bus simultaneously or if a second master joins the bus in the middle of a transfer and wants to control the bus, the I2C bus has an arbitration scheme to guarantee no data corruption.
With I2C, a line (both SDA and SCL) is either driven low or allowed to be pulled high. When a master changes a line state to high, it must sample the line afterwards to make sure it really has been pulled high. If the master samples the SDA bus after setting it high, and the sample shows that the line is low, it knows another master is driving it low. The master assumes it has lost arbitration and waits until it detects a stop condition before making another attempt to start transmitting.
A0, A1 and A2 Chip Address Inputs—The A0, A1 and A2 inputs are used for multiple device operations. The logic levels on these inputs are compared with the corresponding bits in the slave address. The chip is selected if the compare is true. Up to eight devices may be connected to the same bus by using these different Chip Address bit combinations. For applications in which these pins are controlled by a microcontroller or other programmable logic device, the chip address pins must be driven to logic ‘0’ or logic ‘1’ before normal device operation can proceed.
Serial Data (SDA)—This is a bidirectional pin used to transfer addresses and data into and data out of the device. It is an open drain terminal, therefore, the SDA bus requires a pull up resistor to VCC. (typically 2.2 or 4.4 kOhm) For normal data transfer, SDA is allowed to change only during SCL low. Changes during SCL high are reserved for indicating the Start and Stop conditions.
Serial Clock (SCL)—This input is used to synchronize the data transfer from and to the device.
Write-Protect (WP)—This pin must be connected to either VSS or VCC. If tied to VSS, write operations are enabled. If tied to VCC write operations are inhibited but read operations are not affected.
The LabVIEW FPGA Module is a graphical development environment for easily configuring FPGAs on NI reconfigurable I/O (RIO) hardware such at CompactRIO, NI single-board RIO or other reconfigurable hardware to implement functionality that usually requires custom hardware. One such function is implementing digital communication protocols such as I2C.
Using LabVIEW and NI RIO hardware to communicate with I2C devices is simplified with downloadable source code. Download the LabVIEW FPGA I2C IP from the VI Package Manager.
Refer to Understanding I2C with LabVIEW and the USB-8451 to learn how to communicate to I2C devices with the USB-845x and LabVIEW.