Model Based Design for an Elevator HIL Test System Using CompactRIO

Carlos F. Nicolás, Ikerlan

"The modularity and determinism of the CompactRIO system and the flexibility of the LabVIEW FPGA are essential to reproduce in real life the instruments and experiments carried out with the models in the simulations."

- Carlos F. Nicolás, Ikerlan

The Challenge:

Developing an synthetic instrument based on CompactRIO hardware to characterize the efficiency of a lift control on a hardware-in-the-loop (HIL) reactive test bench, reusing a timer model used in simulations.

The Solution:

Generating HDL code from a timer simulation model to create a synthetic instrument, which we integrated with LabVIEW FPGA and other test components on a cRIO-9082 controller, and creating the device’s interface in the test bench control application with LabVIEW software so we can compare the results predicted by the simulation with those obtained with the end product.


Carlos F. Nicolás - Ikerlan
I. Martínez - Ikerlan
I. Ayestarán - Ikerlan
J. M. Martín - Orona


Verifying the maneuver’s control functions on real lifts would require us to build costly test facilities that allow for limited configurations. This is difficult to instrument and offers poor repetition of test results. Real-time HIL lift simulators improve the reproduction of experimental measurements using multiple scenarios and at a lower cost. We adopted a model based design approach for the simulator’s components with the objective of ensuring that the HIL test system reproduced the workings of a real lift with the required accuracy. To validate these models, we designed specific test models to evaluate the simulated lift function. Particularly, we modeled a timer to determine the travel times of the lift cabin. With the proposed method, we reproduced the simulator timer of the HIL system so we could recreate in real time the simulated scenarios and compare the control systems. We checked the results we obtained with the results that had been forecast through the simulations.



Our objective is to reduce time and cost on the lift’s control system by reusing instrument models, already validated in simulations developed in other tools , to build the end product’s verification systems.




The first step is to elaborate lift models that reproduce the dynamics of signals manipulated by a real maneuver. These models are validated with test harnesses that calculate in simulation the entry/exit of the modeled elements. An application expert decides if the achieved accuracy is adequate to emulate a real lift. To win this challenge, we start with a set of lift models written with The MathWorks, Inc. Simulink® software. We created test harnesses and auxiliary instrumentation models with the aim of automatically determining the indirect necessary magnitudes to measure the system’s properties. In particular, we designed a specific timer model to measure the cabin’s travel times (Figure 1).


The timer measures time intervals between speed velocity changes commanded by the lift’s control and stores them in a buffer for later analysis. After a preliminary analysis, we gathered that we needed an FPGA to simulate the lift in real time. Therefore, we customized the models for fixed decimals arithmetic, modifying the calculations. The new models were verified in simulation and compared with the original models and, once validated, we automatically generated HDL code.




To carry out the real-time simulator, we selected a cRIO-9082 controller for its modularity, versatile interface, and temporal determinism. We imported the HDL-coded components to the LabVIEW FPGA project as external IPs (Figure 2) and integrated them with the periferic control IPs and with real-time devices, such as I/O communication modules or buses. We executed the mathematical models in the FPGA in parallel to emulate the signals toward the lift’s maneuver.






We designed the results monitoring elements with LabVIEW, integrating them in a client application so we could monitor and control the CompactRIO simulator (Figure 3). In the case of the timer, this interface is the equivalent in LabVIEW to the Simulink harness model.



We used a cRIO-9082 contoller with two NI 9403 digital I/O low-speed modules and one NI 9401 I/O high-speed module for the real-time simulator. We integrated the simulator in a verification model, together with protection and conditioning components as well as the lift’s maneuver, to be analyzed. We installed the simulator’s monitoring application on a PC, which was connected to the cRIO-9082 with an Ethernet cable.



We developed three components using LabVIEW:

  • A LabVIEW FPGA project to integrate the HDL lift’s mathematical models with the control IPs of the CompactRIO modules
  • A LabVIEW real-time project to communicate the simulator with its environment
  • A LabVIEW application to monitor the lift’s simulator and to analyze, compare, and evaluate the measurements obtained on the tests



We can use the models-based design to evaluate and anticipate the functions to be carried out in a system. We develop test harnesses and auxiliary models during the modeling process, which facilitate the simulation of experiments and the extraction of dynamic characteristics.


We have described how to reuse a timer model to create a synthetic instrument, generating HDL code from the model that we integrated with LabVIEW FPGA “IP Integration Node” blocks in a real-time test system to verify lift’s maneuvers.


The cRIO-9082 controller offers the modularity and execution determinism required by the tests and LabVIEW simplifies the user’s interface programming. CompactRIO and LabVIEW FPGA can reproduce simulated experiments and measurements on models with the real electronic system, reducing costs on the definition and execution of the verification plan.


The modularity and determinism of the CompactRIO system and the flexibility of the LabVIEW FPGA are essential to reproduce in real life the instruments and experiments carried out with the models in the simulations. 


Author Information:

Carlos F. Nicolás
Pº Jose Mª Arizmendiarrieta
2 Mondragon E-20500
Tel: +34 943 712400

Figure 1. Simulation Timer Model
Figure 2. Timer Imported With LabVIEW FPGA
Figure 3. Timer’s User Interface in LabVIEW